Patents by Inventor Roger Lake
Roger Lake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11357331Abstract: Many persons that find it difficult to stand from a chair use powered lift chairs that lift the chair seat in an upward direction. These seats are generally one piece seats and offer only one departure angle that is not suitable for all persons. The adjustable angel chair seat allows the person to choose the best departure angle from the seat for the safest departure from the chair.Type: GrantFiled: February 8, 2021Date of Patent: June 14, 2022Inventor: Eustace Roger Lake
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Patent number: 10758439Abstract: A chair equipped with a pendant controller to help a person rise from a setting position to a standing position with the assistance of arm rests for stability. The chair allows the rear of the seat to be lifted by an electric lifting device mounted directly under the rear of the seat. The front of the seat is hinged to the front frame of the chair allowing the rear of the seat to be moved up to allow the user to reach a height that allows them to exit the chair. The arm rest allows the person to maintain stability during the process.Type: GrantFiled: July 1, 2019Date of Patent: September 1, 2020Inventor: Eustace Roger Lake
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Patent number: 10680403Abstract: Bulk direct transition metal dichalcogenide (TMDC) may have an increased interlayer separation of at least 0.5, 1, or 3 angstroms more than its bulk value. The TMDC may be a bulk direct band gap molybdenum disulfide (MoS2) or a bulk direct band gap tungsten diselenide (WSe2). Oxygen may be between the interlayers. A device may include the TMDC, such as an optoelectronic device, such as an LED, solid state laser, a photodetector, a solar cell, a FET, a thermoelectric generator, or a thermoelectric cooler. A method of making bulk direct transition metal dichalcogenide (TMDC) with increased interlayer separation may include exposing bulk direct TMDC to a remote (aka downstream) oxygen plasma. The plasma exposure may cause an increase in the photoluminescence efficiency of the TMDC, more charge neutral doping, or longer photo-excited carrier lifetimes, as compared to the TMDC without the plasma exposure.Type: GrantFiled: December 16, 2015Date of Patent: June 9, 2020Assignees: University of Southern California, The Regents of the University of CaliforniaInventors: Stephen B. Cronin, Rohan Dhall, Roger Lake, Zhen Li, Mahesh Neupane, Darshana Wickramaratne
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Patent number: 9929338Abstract: Pure spin current devices are provided. The devices include sandwich structures of metal/magnetic insulator/metal. A first current injected in a first metal layer generates a pure spin current. The spin current can be switched between “on” and “off” states by controlling an in-plane magnetization orientation of the magnetic insulator. In the “on” state, the pure spin current is transmitted from the first metal layer to the second metal layer, through the magnetic insulator layer. The pure spin current in the second metal layer induces generation of a second charge current. In the “off” state, the pure spin current is absorbed at the interface between the first metal layer and the metal insulator. Such structures can serve as pure spin current valve devices or provide analog functionality, as rotating the in-plane magnetization provides analog sinusoidal modulation of the spin current.Type: GrantFiled: October 10, 2016Date of Patent: March 27, 2018Assignee: The Regents Of The University Of CaliforniaInventors: Jing Shi, Junxue Li, Yadong Xu, Mohammed Aldosary, Chi Tang, Roger Lake
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Publication number: 20180026422Abstract: Bulk direct transition metal dichalcogenide (TMDC) may have an increased interlayer separation of at least 0.5, 1, or 3 angstroms more than its bulk value. The TMDC may be a bulk direct band gap molybdenum disulfide (MoS2) or a bulk direct band gap tungsten diselenide (WSe2). Oxygen may be between the interlayers. A device may include the TMDC, such as an optoelectronic device, such as an LED, solid state laser, a photodetector, a solar cell, a FET, a thermoelectric generator, or a thermoelectric cooler. A method of making bulk direct transition metal dichalcogenide (TMDC) with increased interlayer separation may include exposing bulk direct TMDC to a remote (aka downstream) oxygen plasma. The plasma exposure may cause an increase in the photoluminescence efficiency of the TMDC, more charge neutral doping, or longer photo-excited carrier lifetimes, as compared to the TMDC without the plasma exposure.Type: ApplicationFiled: December 16, 2015Publication date: January 25, 2018Applicants: UNIVERSITY OF SOUTHERN CALIFORNIA, THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Stephen B. Cronin, Rohan Dhall, Roger Lake, Zhen Li, Mahesh Neupane, Darshana Wickramaratne
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Publication number: 20170104150Abstract: Pure spin current devices are provided. The devices include sandwich structures of metal/magnetic insulator/metal. A first current injected in a first metal layer generates a pure spin current. The spin current can be switched between “on” and “off” states by controlling an in-plane magnetization orientation of the magnetic insulator. In the “on” state, the pure spin current is transmitted from the first metal layer to the second metal layer, through the magnetic insulator layer. The pure spin current in the second metal layer induces generation of a second charge current. In the “off” state, the pure spin current is absorbed at the interface between the first metal layer and the metal insulator. Such structures can serve as pure spin current valve devices or provide analog functionality, as rotating the in-plane magnetization provides analog sinusoidal modulation of the spin current.Type: ApplicationFiled: October 10, 2016Publication date: April 13, 2017Inventors: Jing Shi, Junxue Li, Yadong Xu, Mohammed Aldosary, Chi Tang, Roger Lake
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Patent number: 9197215Abstract: A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits.Type: GrantFiled: May 2, 2014Date of Patent: November 24, 2015Assignee: The Regents of the University of CaliforniaInventors: Alexander A. Balandin, Alexander Khitun, Roger Lake
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Publication number: 20150318856Abstract: A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits.Type: ApplicationFiled: May 2, 2014Publication date: November 5, 2015Applicant: The Regents of the University of CaliforniaInventors: Alexander A. Balandin, Alexander Khitun, Roger Lake
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Publication number: 20080035913Abstract: Molecular resonant tunneling diode (RTD) devices that include a molecular linker or bridge between two carbon nanotube (CNT) leads. Such devices include organic material self-assembled between two leads to yield RTD device behavior without the use of metallization of the organic material. Such devices alleviate the aforementioned problems associated with similar devices. Semiconducting carbon nanotubes (CNTs) may be used, and electrical functionality of the device is provided, not by intrinsic bistable properties of the bridge molecule, but by the crossing of resonant levels with the band edges of the leads.Type: ApplicationFiled: August 14, 2006Publication date: February 14, 2008Applicant: The Regents of the University of CaliforniaInventors: Roger Lake, Khairul Alam, Nicholas A. Burque, Rajeev Pandey
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Patent number: 7303969Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: GrantFiled: August 21, 2001Date of Patent: December 4, 2007Assignee: The Ohio State UniversityInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Publication number: 20050045867Abstract: Disclosed herein are nanoscale heterojunctions and methods of making and using thereof. The heterojunctions comprise at least one carbon nanotube with at least one nanostructure such as a quantum dot connected, immobilized, attached, or affixed thereto. The carbon nanotubes may be single walled, multi-walled, or a combination of both. The nanostructure is preferably a quantum dot such as a ZnS capped CdSe core. The carbon nanotube heterojunctions may be employed in various nanoscale electronics and optoelectronic devices and multilayered systems including light emitting diodes, single electron transistors, spintronic devices, field emission flat panel displays, vacuum microelectronic sources, biosensors, random access memories, spin valves, and the like.Type: ApplicationFiled: October 30, 2003Publication date: March 3, 2005Inventors: Cengiz Ozkan, Sathyajith Ravindran, Roger Lake, Mihrimah Ozkan, Natan Portney
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Patent number: 6803598Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: GrantFiled: May 5, 2000Date of Patent: October 12, 2004Assignee: University of DelawareInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel
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Publication number: 20030049894Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.Type: ApplicationFiled: August 21, 2001Publication date: March 13, 2003Applicant: University of DelawareInventors: Paul R. Berger, Phillip E. Thompson, Roger Lake, Karl Hobart, Sean L. Rommel