Abstract: A vertical farming structure having vertical grow towers and associated conveyance mechanisms for moving the vertical grow towers through a controlled environment, while being exposed to controlled conditions, such as lighting, airflow, humidity and nutritional support. The present disclosure describes a reciprocating cam mechanism that provides a cost-efficient mechanism for conveying vertical grow towers in the controlled environment. The reciprocating cam mechanism can be arranged to increase the spacing of the grow towers as they are conveyed through the controlled environment to index the crops growing on the towers. The present disclosure also describes a tower shuttle mechanism that provides operational flexibility by decoupling the loading and unloading operations of the grow towers from the vertical farming structure and, therefore, allowing multiple grow towers to be extracted for harvesting in a batch process before loading new grow towers into the vertical farming structure in a separate process.

Abstract: A vertical farming structure having vertical grow towers and associated conveyance mechanisms for moving the vertical grow towers through a controlled environment, while being exposed to controlled conditions, such as lighting, airflow, humidity and nutritional support. The present disclosure describes a reciprocating cam mechanism that provides a cost-efficient mechanism for conveying vertical grow towers in the controlled environment. The reciprocating cam mechanism can be arranged to increase the spacing of the grow towers as they are conveyed through the controlled environment to index the crops growing on the towers. The present disclosure also describes a tower shuttle mechanism that provides operational flexibility by decoupling the loading and unloading operations of the grow towers from the vertical farming structure and, therefore, allowing multiple grow towers to be extracted for harvesting in a batch process before loading new grow towers into the vertical farming structure in a separate process.

Abstract: An integrated circuit apparatus includes a silicon-on-insulator (SOI) substrate comprising a silicon layer overlying an insulator layer; a first silicon fin region formed in a first region of the silicon layer, the first silicon fin region comprising a first source region, a first drain region, and a first channel region; a second silicon fin region formed in a second region of the silicon layer, the second silicon fin region comprising a second source region, a second drain region, and a second channel region; a gate dielectric layer formed on the first, second, and third surface regions of the first silicon fin region, and on the third and fourth surface regions of the second silicon fin region; a dual-gate FinFET, comprising the second drain, source and channel regions in the second silicon fin region; and a tri-gate FinFET, comprising the first drain, source and channel regions.

Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Abstract: An earth-boring tool includes a body having a shank and a crown, a plurality of blades protruding from the crown of the body and extending at least substantially along a longitudinal length of the crown of the body, each blade extending radially outward and defining a respective radially outermost gage surface. The earth-boring tool further includes at least one rotatable cutting structure assembly including a leg and a rotatable cutting structure rotatably coupled to the leg. The earth-boring tool also includes at least one stabilizing structure secured to the crown of the body between an end of the leg opposite the rotatable cutting structure and the shank of the body, the at least one stabilizing structure being at least substantially circumferentially aligned with the leg of the at least one rotatable cutting structure assembly along a circumference of the crown of the body.

Abstract: According to an example, coordinates in a coordinate space of a display device at which a line is to be displayed may be determined. A first set of intensity profile discs corresponding to the determined coordinates and a second set of intensity profile discs having inverted intensity profiles from the first set of intensity profile discs may be identified. The identified second set of intensity profile discs may be displayed at the determined coordinates on the display device and the identified first set of intensity profile discs may be displayed over the displayed second set of intensity profile discs on the display device.

Abstract: An earth-boring tool includes a body having a shank and a crown, a plurality of blades protruding from the crown of the body and extending at least substantially along a longitudinal length of the crown of the body, each blade extending radially outward and defining a respective radially outermost gage surface. The earth-boring tool further includes at least one rotatable cutting structure assembly including a leg and a rotatable cutting structure rotatably coupled to the leg. The earth-boring tool also includes at least one stabilizing structure secured to the crown of the body between an end of the leg opposite the rotatable cutting structure and the shank of the body, the at least one stabilizing structure being at least substantially circumferentially aligned with the leg of the at least one rotatable cutting structure assembly along a circumference of the crown of the body.

Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Abstract: According to an example, coordinates in a coordinate space of a display device at which a line is to be displayed may be determined. A first set of intensity profile discs corresponding to the determined coordinates and a second set of intensity profile discs having inverted intensity profiles from the first set of intensity profile discs may be identified. The identified second set of intensity profile discs may be displayed at the determined coordinates on the display device and the identified first set of intensity profile discs may be displayed over the displayed second set of intensity profile discs on the display device.

Abstract: A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

Abstract: A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

Abstract: A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

Abstract: A liquid crystal on silicon (LCOS) device includes a semiconductor substrate, a metal-oxide semiconductor (MOS) device layer overlying the semiconductor substrate, a planarized interlayer dielectric layer overlying the MOS device layer, a plurality of recessed regions formed within a portion of the interlayer dielectric layer, a metal layer filling each of the recessed regions to form a plurality of respective electrode plates corresponding to each of the recessed regions. The LCOS device further includes a protective layer overlying a surface of each of the plurality of electrode plates, a liquid crystal film overlying the protective layer, and a mirror finish formed on each of the surface of the electrode plates for reflecting light. The mirror finish is substantially free from dishes and scratches from a chemical mechanical polishing process.

Abstract: A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern.

Abstract: The invention relates to a system for testing heart valve leaflets. The system includes a leaflet support assembly with a support post for receiving and supporting a leaflet to be tested, the post being disposed in a target region of the support assembly. The system also has a transmitter assembly that includes a light source and is configured and arranged to direct light from the light source onto the target region. The system further includes a receiver assembly that has an image sensor configured and arranged to sense an image of the target region and generate image information indicative of the sensed image, such as leaflet droop.

Abstract: A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern.

Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.

Abstract: A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern.

Abstract: A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.