Patents by Inventor Roger M. Kieckhafer

Roger M. Kieckhafer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4980857
    Abstract: A task communicator for each node in a multiple node processing system having a data memory storing data received from a voter interface which is used for the execution of tasks by an associated applications processor, a next task register storing the identification code of the next task to be executed by the applications processor received from a scheduler through a scheduler interface. An input handler passes the identification code of the next task and the data required for the execution of that task to an input FIFO register interfacing the applications processor. An output FIFO register temporarily stores the data generated by the applications processor and an output handler generates inter-node messages containing data stored in the output FIFO and passes these inter-node messages to a transmitter through a transmitter interface for transmission to all of the other nodes in the processing system.
    Type: Grant
    Filed: June 7, 1989
    Date of Patent: December 25, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kieckhafer, Alan M. Finn
  • Patent number: 4972415
    Abstract: A voter subsystem for a multiple node fault tolerant system having an upper medial value sorter for sorting a plurality of received values to generate an upper medial value and a lower medial value sorter for sorting the same plurality of received values to generate a lower medial value. An averaging circuit adds the upper and lower medial values then divides by two to generate a voted value. A deviance checker checks each of the plurality of received values against the voted value to generate a deviance error for each received value which differed from the voted value by a predetermied amount. A loader loads the plurality of received values into the upper and lower medial value sorters and the deviance checker bit-by-bit, starting from the most significant bit positions through the least significant bit positions. The upper and lower medial value sorters and deviance checker process the received values on-the-fly in the order they are received.
    Type: Grant
    Filed: June 7, 1989
    Date of Patent: November 20, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kieckhafer, Alan M. Finn
  • Patent number: 4914657
    Abstract: An operations controller for a multiple node fault tolerant processing system having a transmitter for transmitting inter-node messages, a plurality of receivers, each receiving inter-node messages from only one of the nodes and a message checker for checking each received message for physical and logical errors. A fault tolerator assembles all of the errors detected and decides which nodes are faulty based on the number and severity of the detected errors. A voter generates a voted value for each value which is received from the other nodes which is stored in a data memory by a task communicator. A scheduler selects the tasks to be executed by an applications processor which is passed to the task communicator. The task communicator passes the selected task and the data required for the execution of that task to the applications processor and transmits the data resulting from that task to all of the nodes in the system.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: April 3, 1990
    Assignee: Allied-Signal Inc.
    Inventors: Chris J. Walter, Roger M. Kieckhafer, Alan M. Finn
  • Patent number: 4816989
    Abstract: A synchronizer for each node in a multiple node processing system having a message interface for receiving sync and pre-sync time-dependent message, counter means for generating a local time, a time stamp memory having an entry for each node in the multiple node processing system, a time stamper responsive to receiving a time-dependent message from a node for storing the local time in the entry of said time stamp memory for that node to generate a time stamp.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: March 28, 1989
    Assignee: Allied-Signal Inc.
    Inventors: Alan M. Finn, Roger M. Kieckhafer, Chris J. Walter
  • Patent number: 4805107
    Abstract: A task scheduler for a fault tolerant multiple node processing system having a task activity list storing a set of application tasks, a priority scan list storing a selected portion of the set of application tasks, a completion status list also storing the same selected portion of the set of application tasks. A wake-up sequencer transfers the application tasks from the task activity list to the priority scan list, and a priority scanner transfers the application tasks ready for execution from the priority scan list to a selection queue. A next task selector selects the next application task that its node will execute, and a task started register stores the identity of the application tasks completed by the other nodes. A task interactive consistency (TIC) handler updates the status of the application tasks stored in the task activity list, the priority scan list, and the completion status list in response to messages received from the other nodes identifying which nodes completed tasks.
    Type: Grant
    Filed: April 15, 1987
    Date of Patent: February 14, 1989
    Assignee: Allied-Signal Inc.
    Inventors: Roger M. Kieckhafer, Alan M. Finn, Chris J. Walter