Abstract: Various exemplary embodiments relate to a method of evaluating cloud network performance. The method includes: measuring a latency of a plurality of service requests in a cloud-network; determining a mean latency; and determining a variance of the plurality of service requests; comparing the mean latency to a first threshold; comparing the variance to a second threshold; and determining that the cloud-network is deficient if either the mean latency exceeds the first threshold or the variance exceeds the second threshold.

Abstract: The direct memory access device and method of the present invention uses an event calendar, an expired event queue of a fixed size, a calendar scanner, and an event mover. The event calendar stores an event in a linked list. The expired event queue stores an event that has already expired from the event calendar. The calendar scanner automatically scans the event calendar without management by a central processing unit (CPU). The event mover moves an event from the event calendar to the expired event queue without management by the CPU. The method provides for storing the event in the linked list, automatically scanning the event calendar without management by the CPU, moving the event from the event calendar to an expired event queue of a fixed size without management by the CPU, and storing the event that has already expired from the event calendar.

Abstract: An off-load for processing a data frame containing information has a memory for storing information on a plurality of processing paths. A processor in the off-load engine determines which processing path the data frame is to be processed. Each one of a plurality of processing engines processes the data frame depending on whether the processing engine is within the determined processing path. Some of the processing engines are implemented in hardware and/or data frame type specific software and others makes use of generic software. In some embodiments, the data frame is also parsed for further processing by the processing engines. In some embodiments, a static header is also pre-pended to the data frame to allow easy access to information associated with the data frame by the processing engines.

Abstract: A system and method for a parallel CRC calculation is provided. A set of parallel inputs are loaded into a control register, and this control register is then used with a parallel table look-up operation to look up CRC entries for each of the inputs using a single instruction. This is repeated until each input has been processed completely to produce a complete CRC. The parallel table look-up operation may be executed using the PowerPC Altivec vperm instruction.

Abstract: Methods and computer readable media are provided for implementing state machines in parallel. A control vector is generated from current state and input bits. This vector is then used to determine the next state and any output bits for each of a plurality of state machines in parallel. In some implementations, the Altivec vperm instruction is used to perform a parallel table look-up.

Abstract: The direct memory access device and method of the present invention uses an event calendar, an expired event queue of a fixed size, a calendar scanner, and an event mover. The event calendar stores an event in a linked list. The expired event queue stores an event that has already expired from the event calendar. The calendar scanner automatically scans the event calendar without management by a central processing unit (CPU). The event mover moves an event from the event calendar to the expired event queue without management by the CPU. The method provides for storing the event in the linked list, automatically scanning the event calendar without management by the CPU, moving the event from the event calendar to an expired event queue of a fixed size without management by the CPU, and storing the event that has already expired from the event calendar.

Abstract: A scheduler in, for example, an off-load engine reports events for processing data frames to processing engines. Each event to report has associated to it an event information to report to a respective processing engine for processing, for example, a data frame. Responsive to a prompt having a specified time, a processor looks up the event information to report at the specified time in one or more memories. For each event information to report at the specified time, at least some of the event information is forwarded to the respective processing engine. A state machine is used as the processor to implement functionality of the scheduler in hardware thereby providing off-loading of processing in the off-load engine from software to hardware.

Abstract: An apparatus produces a combined data frame in DHO (Diversity Hand-Off) from data frames each having one or more payload sequences. Each payload sequence has associated with it one or more quality indicators. The quality indicators may be for example a CRCI (Cyclic Redundancy Code Indicator) for the payload sequence and a QE (Quality Estimate) of the data frame having the payload sequence. For corresponding payload sequences from each of the data frames a bit sequence is defined for each corresponding payload sequence with the quality indicators occupying one or more consecutive bits within the bit sequence. A processor selects, as a payload sequence for the combined data frame, one of the corresponding payload sequences on the basis of the bit sequences. The apparatus is implemented in software or in hardware.

Abstract: A method and apparatus are used to generate outputs according to a ciphering algorithm which for each of the outputs operates on a respective input using a respective key. The ciphering algorithm has a plurality of rounds in which functions are evaluated. For a least one of the functions, outputs are generated by looking up at least one look-up table with each look-up table being looked-up in parallel using respective inputs. Different methods for parallel table look-up are provided. The methods allows the ciphering algorithm to be implemented partially or entirely in parallel. An example parallel implementation involves the Kasumi algorithm in which S7 and S9 functions are evaluated in parallel for a plurality of inputs using vector instructions on an SIMD (Single Instruction Multiple Data) architecture.