Abstract: A method for testing a semiconductor assembly includes: in a three-dimensional (3D) multi-die assembly with a first die and a second die coupled by hybrid bond pad interconnects, operating a mission-mode datapath between the dies using bidirectional general purpose input output (GPIO) pads configured for a first signal direction in mission mode. In test mode, at least a subset of the GPIO pads operate in a second signal direction different from the first signal direction to form at least one on-die loopback path. Test data is injected into the mission-mode datapath at an injection point not on a critical timing path for mission-mode operation of the mission-mode datapath. Received test data is monitored through the on-die loopback path to detect at least one interconnect defect associated with the hybrid bond pad interconnects.

Abstract: A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

Abstract: A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.