Abstract: Some examples described herein provide for display image data reliability and safety, for example end-to-end safety methods, apparatuses, and systems for display systems. One example includes a method, including replacing video frames from input video streams with a set of test frames. The method further includes generating an alpha-blended video stream based on the set of test frames and the input video streams. The method further includes generating and inserting cyclic redundancy check (CRC) information for the set of test frames into secondary data packets associated with the alpha-blended video stream. The method further includes processing the set of test frames and video frames by a display controller to generate an output video stream. The method further includes performing an error detection procedure for the set of test frames using the CRC information to detect an error associated with the set of video frames.

Abstract: A sizer for cooling an extrudate, which includes a core and a housing. The core includes an extrusion channel which accommodates the extrudate, a core cooling channel, and a core vacuum channel in fluid communication with the extrusion channel. The housing includes a housing cooling channel and a housing vacuum channel. The core cooling channel is in fluid communication with the housing cooling channel, and the core vacuum channel is in fluid communication with the housing vacuum channel.

Abstract: Some examples described herein provide for display image data reliability and safety, for example end-to-end safety methods, apparatuses, and systems for display systems. One example includes a method, including replacing video frames from input video streams with a set of test frames. The method further includes generating an alpha-blended video stream based on the set of test frames and the input video streams. The method further includes generating and inserting cyclic redundancy check (CRC) information for the set of test frames into secondary data packets associated with the alpha-blended video stream. The method further includes processing the set of test frames and video frames by a display controller to generate an output video stream. The method further includes performing an error detection procedure for the set of test frames using the CRC information to detect an error associated with the set of video frames.

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

Abstract: A sizer for cooling an extrudate, which includes a clad core and a housing. The clad core includes an extrusion channel which accommodates the extrudate, and a core vacuum port in fluid communication with the extrusion channel. The housing includes a cooling channel and a housing vacuum channel. The cooling channel does not exist in the clad core and is adapted to circulate a coolant through the housing.

Abstract: A sizer for cooling an extrudate, which includes a core and a housing. The core includes an extrusion channel which accommodates the extrudate, a core cooling channel, and a core vacuum channel in fluid communication with the extrusion channel. The housing includes a housing cooling channel and a housing vacuum channel. The core cooling channel is in fluid communication with the housing cooling channel, and the core vacuum channel is in fluid communication with the housing vacuum channel.

Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

Abstract: A sizer for cooling an extrudate includes a core and a housing. The core includes an extrusion channel which accommodates the extrudate, a core cooling channel, and a core vacuum channel in fluid communication with said extrusion channel. The housing includes a housing cooling channel, a housing vacuum channel, a cooling intake, and a cooling exhaust. The housing cooling and vacuum channels having curved segments. The cooling intake and exhaust being in fluid communication with said housing cooling channel.

Abstract: A sizer for cooling an extrudate includes a core and a housing. The core includes an extrusion channel which accommodates the extrudate, a core cooling channel, and a core vacuum channel in fluid communication with said extrusion channel. The housing includes a housing cooling channel, a housing vacuum channel, a cooling intake, and a cooling exhaust. The housing cooling and vacuum channels having curved segments. The cooling intake and exhaust being in fluid communication with said housing cooling channel.

Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

Abstract: Methods, systems and apparatuses may provide for technology that includes a chip having a first die including a first processing logic to execute a first application instance and generate a first output of the first application instance, and a second processing logic to execute a second application instance and generate a second output of the second application instance. The chip may also include a second die coupled to the first die, wherein the second die includes a safety monitor detect a condition associated with one or more of an error in the first output, an error in the second output, or a discrepancy between the first output and the second output. The safety monitor may also initiate a transition of the chip into a safe state in response to the condition.

Abstract: A programmable integrated circuit may implement a safety function in a first region and a non-safety function in a second region of the programmable integrated circuit. The safety function may require that periodic tests verify the integrity of the programmable integrated circuit during safety test intervals. For this purpose, the programmable integrated circuit may halt the operation of the safety function, partially reconfigure the first region by loading a test function, and execute the test function, while the non-safety function in the second region continues to operate. In the event that the test function executed successfully without finding any defects, the programmable integrated circuit may partially reconfigure the first region by re-loading the safety function. Additional tests may be performed if the test function detected problems with the integrity of the programmable integrated circuit.

Abstract: A video processing device has an input for receiving video data, at least one processing circuit, for generating processed video data from the received video data, and a memory, for receiving the processed video data. An output circuit reads the processed video data from the memory, and generates frames of data including at least the processed video data. In order to be able to operate with an output clock frequency that may differ from the ideal output clock frequency, it is possible to vary the frame size, that is, the number of pixels of data in a frame. If an amount of processed video data stored in the memory exceeds an upper threshold, then the frame size can be reduced by reducing the number of pixels of blanking data in the output frame, thereby increasing the rate at which data is read from the memory.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

Abstract: A method and apparatus for configuring a digital system having a programmable logic device and embedded logic from a configuration source that supplies a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.

Abstract: A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.