Abstract: A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.

Abstract: A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.

Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.

Abstract: A power metal-oxide-semiconductor (MOS) field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die, A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material, A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to the grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract: A power MOS field effect transistor (FET) has a plurality of transistor cells, each cell having a source region and a drain region to be contacted through a surface of a silicon wafer die. A first dielectric layer is disposed on the surface of the silicon wafer die and a plurality of grooves are formed in the first dielectric layer above the source regions and drain regions, respectively and filled with a conductive material. A second dielectric layer is disposed on a surface of the first dielectric layer and has openings to expose contact areas to said grooves. A metal layer is disposed on a surface of the second dielectric layer and filling the openings, wherein the metal layer is patterned and etched to form separate metal wires connecting each drain region and each source region of the plurality of transistor cells, respectively through the grooves.

Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.