Abstract: A multi-chip apparatus is disclosed. In one form, the apparatus includes a carrier having a number of integrated circuit chips electrically coupled in a communications ring. The communications ring has carrier portions on the carrier and chip portions traversing the respective chips, permitting the communications ring carrier portions to be substantially straight, whereas at least one of the chip portions has a turn, enabling closure of the ring. In another aspect, the chips include respective regeneration circuitry interposed in the respective chip portions of the communications ring, for regenerating communications signals traversing the respective chips on the respective chip portions of the ring.

Abstract: A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block.

Abstract: The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

Abstract: An integrated circuit chip has a first i/o set associated with a first edge of the chip and a second i/o set associated with a second edge of the chip. The first i/o set has a physical symmetry with respect to the second i/o set, to facilitate a number of the chips being interconnected in a ring to one another on a multi-chip module, with the chips symetrically disposed thereon. The chip has a bus interconnecting the first and second i/o sets for transmitting signals across the chip. The bus has regeneration circuitry for regenerating said signals traversing the chip.

Abstract: A floating point processing system and method of operation are disclosed. Single word precision denormalized operands and also misaligned operands are detected while such operands are being loaded into the first stage of a pipelined floating point unit. Such operands are aligned to a double word boundary and/or single word operands are normalized by a processing stages inserted into the pipe ahead of the first stage of the pipelined floating point unit thereby entering a one stage delay. In this way, misaligned operands and single word denormalized operands can be processed without the need for example to cancel the instruction, execute a normalize or alignment instruction and then re-launch the original instruction.