Patents by Inventor Roger Ng

Roger Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11144687
    Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 12, 2021
    Assignee: XILINX, INC.
    Inventors: Pramod Chandraiah, Roger Ng, Alain Darte, Radharamanan Radhakrishnan, Peter Frey, Kumar Deepak
  • Patent number: 11042564
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating transaction associations in a waveform display. One of the methods includes receiving data representing a main signal for a selected transaction in a waveform display, the main signal including a plurality of main signal events. A search is performed for data representing one or more side signals associated with the main signal for the selected transaction, each side signal including a plurality of side signal events representing other transactions that are associated with the main signal at a time indicated by a corresponding main signal event. A visual indication is generated within the waveform display of an association between the selected transaction and one or more transactions identified by the one or more side signals associated with the main signal for the selected transaction.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 22, 2021
    Assignee: Xilinx, Inc.
    Inventors: David K. Liddell, Roger Ng, Kumar Deepak
  • Patent number: 10762263
    Abstract: A method includes inputting to a computer processor a search value. Bit values of bit element signals of a bus at a current time are determined time-ordered value pairs of timestamps and associated bit values of the bit element signals. Whether the bit values at the current time match values of corresponding bits of the search value is determined from the time-ordered value pairs. Data indicative of the current time and bit values of the bit element signals is output if the bit values at the current time match the search value. If any of the bit values at the current time do not match the search value, the current time is advanced to a later time indicated by a time-ordered value pair not matched to the search value and having a latest timestamp of the bit element signals that do not match corresponding bits of the search value.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Roger Ng, David K. Liddell
  • Patent number: 10740210
    Abstract: Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 11, 2020
    Assignee: Xilinx, Inc.
    Inventors: Paul R. Schumacher, Kumar Deepak, Roger Ng, David K. Liddell
  • Patent number: 10642811
    Abstract: A waveform simulation system with a waveform database architecture satisfies different requirements of different waveform simulation tools. The waveform simulation system includes a waveform database configured to store one or more mappings that map one or more design objects to one or more memory addresses. The waveform simulation system also includes a packet processing module configured to receive simulation data from a simulation tool. The packet processing module is configured to translate the simulation data into translated simulation data that is independent of implementation details of the one or more design objects, based at least in part on the one or more mappings. In some cases, the translated simulation data may include event data stored in the waveform database.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 5, 2020
    Assignee: XILINX, INC.
    Inventors: David K. Liddell, Roger Ng, Hem C. Neema
  • Patent number: 9695529
    Abstract: A fully fashion knitted outer covering made by using a method for generation of contour fit 3D fully fashion knitted outer covering pattern based on 3D exterior data of an object. The method comprises the following steps: digitizing an individual to create a 3D object data cloud; automatically and/or manually recognizing object's exterior landmarks; extracting the object's exterior measurements; calculating the outer covering pattern block of the digitized surface of the object according to the extracted object's exterior measurements including geodesic measurements; transforming the outer covering block to 3D weft knitted outer covering pattern by introducing horizontal and/or vertical darts; and translating the modified knitted outer covering pattern to knitting diagrams and/or instructions, which can then be transferred to knitwear CAD system to control the automatic knitting machine to knit the required knitted outer covering.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: July 4, 2017
    Assignee: Artlink International Development Limited
    Inventors: Keng Po Roger Ng, Tin-yee Clement Lo, Chun Ting Cheung, Ting Man Lam, Jinyun Zhou
  • Patent number: 9681694
    Abstract: A fully fashion knitwear made by using a method for generation of contour fit three-dimensional (3D) fully fashion knitwear pattern based on 3D body data of an individual. The method comprises the following steps: digitizing an individual to create a 3D body data cloud; automatically recognizing body landmarks; extracting the body measurements; calculating the garment pattern block of the digitized surface of the individual according to the extracted body measurements including geodesic (minimal distance) measurements; transforming the garment block to 3D weft knitwear pattern by introducing horizontal and/or vertical darts; and translating the modified knitwear pattern to knitting diagrams and/or instructions, which can then be transferred manually to knitwear CAD system to control the automatic knitting machine to knit the required knitwear.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 20, 2017
    Assignee: Artlink International Development Limited
    Inventors: Keng Po Roger Ng, Tin-yee Clement Lo, Chun Ting Cheung, Ting Man Lam, Jinyun Zhou
  • Publication number: 20160309823
    Abstract: A fully fashion knitted outer covering made by using a method for generation of contour fit 3D fully fashion knitted outer covering pattern based on 3D exterior data of an object. The method comprises the following steps: digitizing an individual to create a 3D object data cloud; automatically and/or manually recognizing object's exterior landmarks; extracting the object's exterior measurements; calculating the outer covering pattern block of the digitized surface of the object according to the extracted object's exterior measurements including geodesic measurements; transforming the outer covering block to 3D weft knitted outer covering pattern by introducing horizontal and/or vertical darts; and translating the modified knitted outer covering pattern to knitting diagrams and/or instructions, which can then be transferred to knitwear CAD system to control the automatic knitting machine to knit the required knitted outer covering.
    Type: Application
    Filed: April 18, 2016
    Publication date: October 27, 2016
    Inventors: Keng Po Roger Ng, Tin-yee Clement Lo, Chun Ting Cheung, Ting Man Lam, Jinyun Zhou
  • Publication number: 20160309822
    Abstract: A fully fashion knitwear made by using a method for generation of contour fit three-dimensional (3D) fully fashion knitwear pattern based on 3D body data of an individual. The method comprises the following steps: digitizing an individual to create a 3D body data cloud; automatically recognizing body landmarks; extracting the body measurements; calculating the garment pattern block of the digitized surface of the individual according to the extracted body measurements including geodesic (minimal distance) measurements; transforming the garment block to 3D weft knitwear pattern by introducing horizontal and/or vertical darts; and translating the modified knitwear pattern to knitting diagrams and/or instructions, which can then be transferred manually to knitwear CAD system to control the automatic knitting machine to knit the required knitwear.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 27, 2016
    Inventors: Keng Po Roger Ng, Tin-yee Clement Lo, Chun Ting Cheung, Ting Man Lam, Jinyun Zhou
  • Patent number: 8640064
    Abstract: Processing a circuit design specified in a hardware description language (HDL) can include, for each of a plurality of nets of the circuit design, creating a trace memory structure, using a processor, during compilation of the HDL circuit design. Each trace memory structure can include trace properties indicating whether tracing is active for the net. A transaction function can be generated during compilation for each net. The transaction function can be configured to invoke tracing for each net during simulation of the circuit design according to an evaluation of the trace properties for the net.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: January 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: David K. Liddell, Roger Ng
  • Patent number: 7784005
    Abstract: Various approaches for displaying design data that implements an electronic design in lookup tables (LUTs) of a programmable logic device are disclosed. In one approach, a user is presented for selection at least two selectable modes for displaying a function performed by a LUT that is configurable with the design data to implement a function of the electronic design. The modes have associated, different formats for display of a function. In response to selection of an object that represents a first LUT having an assigned initialization value and in response to selection of one of the modes, the function performed by the first LUT, as defined by the initialization value, is displayed in the format associated with the selected mode.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: August 24, 2010
    Assignee: Xilinx, Inc.
    Inventor: Roger Ng