Abstract: Disclosed approaches for rendering event data from subsystems in different clock domains according to a system-level timeline include, for each of multiple subsystems, sampling a system timer in a first clock domain for a first timestamp by a host processor. A host processor requests a subsystem timestamp from a subsystem timer in each of the subsystems. The subsystem timestamp is associated with the first timestamp, and the subsystem timer operates in a clock domain different from the first clock domain. The host processor translates timestamps in traced event data of the subsystems to a timeline of the system timer using the first timestamp and associated subsystem timestamps.

Abstract: Disclosed approaches for rendering event data from subsystems in different clock domains according to a system-level timeline include, for each of multiple subsystems, sampling a system timer in a first clock domain for a first timestamp by a host processor. A host processor requests a subsystem timestamp from a subsystem timer in each of the subsystems. The subsystem timestamp is associated with the first timestamp, and the subsystem timer operates in a clock domain different from the first clock domain. The host processor translates timestamps in traced event data of the subsystems to a timeline of the system timer using the first timestamp and associated subsystem timestamps.

Abstract: Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.

Abstract: Hardware event trace windowing for a data processing array includes executing a user design using a plurality of active tiles of a data processing array disposed in an integrated circuit. A trace start condition is detected subsequent to a start of execution of the user design. In response to the trace start condition, trace data is generated using one or more of the plurality of active tiles of the data processing array. A trace stop condition is detected during execution of the user design. In response to the trace stop condition, the generating the trace data by the one or more of the plurality of active tiles is discontinued.

Abstract: Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.

Abstract: Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating transaction associations in a waveform display. One of the methods includes receiving data representing a main signal for a selected transaction in a waveform display, the main signal including a plurality of main signal events. A search is performed for data representing one or more side signals associated with the main signal for the selected transaction, each side signal including a plurality of side signal events representing other transactions that are associated with the main signal at a time indicated by a corresponding main signal event. A visual indication is generated within the waveform display of an association between the selected transaction and one or more transactions identified by the one or more side signals associated with the main signal for the selected transaction.

Abstract: A method includes inputting to a computer processor a search value. Bit values of bit element signals of a bus at a current time are determined time-ordered value pairs of timestamps and associated bit values of the bit element signals. Whether the bit values at the current time match values of corresponding bits of the search value is determined from the time-ordered value pairs. Data indicative of the current time and bit values of the bit element signals is output if the bit values at the current time match the search value. If any of the bit values at the current time do not match the search value, the current time is advanced to a later time indicated by a time-ordered value pair not matched to the search value and having a latest timestamp of the bit element signals that do not match corresponding bits of the search value.

Abstract: Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.

Abstract: A waveform simulation system with a waveform database architecture satisfies different requirements of different waveform simulation tools. The waveform simulation system includes a waveform database configured to store one or more mappings that map one or more design objects to one or more memory addresses. The waveform simulation system also includes a packet processing module configured to receive simulation data from a simulation tool. The packet processing module is configured to translate the simulation data into translated simulation data that is independent of implementation details of the one or more design objects, based at least in part on the one or more mappings. In some cases, the translated simulation data may include event data stored in the waveform database.

Abstract: Processing a circuit design specified in a hardware description language (HDL) can include, for each of a plurality of nets of the circuit design, creating a trace memory structure, using a processor, during compilation of the HDL circuit design. Each trace memory structure can include trace properties indicating whether tracing is active for the net. A transaction function can be generated during compilation for each net. The transaction function can be configured to invoke tracing for each net during simulation of the circuit design according to an evaluation of the trace properties for the net.

Abstract: Various approaches for displaying design data that implements an electronic design in lookup tables (LUTs) of a programmable logic device are disclosed. In one approach, a user is presented for selection at least two selectable modes for displaying a function performed by a LUT that is configurable with the design data to implement a function of the electronic design. The modes have associated, different formats for display of a function. In response to selection of an object that represents a first LUT having an assigned initialization value and in response to selection of one of the modes, the function performed by the first LUT, as defined by the initialization value, is displayed in the format associated with the selected mode.