Patents by Inventor Roger P. Ang

Roger P. Ang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143139
    Abstract: A proximity-enabled machine control system includes a user mobile device having a processor, a touch sensitive screen coupled to the processor, and non-transitory computer readable media with code segments executable on the processor for: (a) determining if the user mobile device is within a proximity zone of a machine: (b) displaying on the touch sensitive screen at least one machine control button for the machine; (c) detecting an activation of the at least one machine control button by the user; and (d) developing a machine control signal to control the machine.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventors: Jeffrey M. White, Roger P. Ang
  • Publication number: 20140258963
    Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths is described. In one embodiment, the method to layout an integrated circuit, the method comprises routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit, and placing a third cell of the integrated circuit after said routing the wire to connect the first cell and the second cell.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: Synopsys, Inc.
    Inventors: Roger P. ANG, Ken R. McELVAIN, Kenneth S. McELVAIN
  • Patent number: 8732645
    Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: May 20, 2014
    Assignee: Synopsys, Inc.
    Inventors: Roger P. Ang, Ken R. McElvain, Kenneth S. McElvain
  • Publication number: 20080201678
    Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 21, 2008
    Inventors: Roger P. Ang, Ken R. McElvain, Kenneth S. McElvain
  • Patent number: 7350173
    Abstract: Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: March 25, 2008
    Assignee: Synplicity, Inc.
    Inventors: Roger P. Ang, Ken R. McElvain, Kenneth S. McElvain