Abstract: A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and is coupled between the output of the comparator and the input of the drive circuit. The feedback circuit terminates a pulse output from the drive circuit when the pulse voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances.

Abstract: A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

Abstract: A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and is coupled between the output of the comparator and the input of the drive circuit. The feedback circuit terminates a pulse output from the drive circuit when the pulse voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances.

Abstract: A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.

Abstract: Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.

Abstract: This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.

Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.

Abstract: A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signal connection locations formed in columns orthogonal to a chip edge or segment of the chip perimeter. Signal connections in a column are spaced at a first pitch and columns of signal connections are spaced at a second pitch. Power connections corresponding to different power supply voltages are provided between columns of signal connections and along rows which are centered between rows of signal connections generally parallel to an edge of a chip. Power distribution layers may be formed as a mesh which extends in under the chip in alignment with power connections to the chip and beyond the perimeter of the chip, as well to provide multiple low-impedance power delivery paths to improve noise immunity.

Abstract: A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the second I/O port is connected to an I/O port of a second digital circuit operating at a relatively high supply voltage. This channel passes communication signals in each direction between the first and second digital circuit. A latching circuit comprising a P Channel FET is biased by the relatively high voltage supply, has an output connected to the second I/O port, and has a control input.