Patents by Inventor Roger S. Countryman

Roger S. Countryman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5463353
    Abstract: A voltage controlled oscillator (VCO) 16 generates a periodic clock signal without the use any resistors. Therefore, the described VCO may be advantageously incorporated into devices fabricated with semiconductor processes without special resistor-base design constraints.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: October 31, 1995
    Assignee: Motorola, Inc.
    Inventors: Roger S. Countryman, Jose Alvarez
  • Patent number: 5448182
    Abstract: A CMOS driver circuit (20) has a high impedance driver (30) and a low impedance driver (36) connected to the near end of a transmission line (43). The output impedance of the high impedance driver (30) matches the characteristic impedance of the transmission line (43). As a digital signal from the CMOS driver circuit (20) transitions from one logic state to another, the low impedance driver (30) drives the transmission line (43) until a predetermined voltage before the signal reaches its steady state voltage. A sensing circuit (24) senses when the predetermined voltage is reached, and in response, provides a control signal to deactivate the low impedance driver (36). The high impedance driver (30) completes the signal transition. The high impedance driver (30) absorbs the reflected waves from the far end of the transmission line (43), reducing the effects of ringing, and increasing noise immunity.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: September 5, 1995
    Assignee: Motorola Inc.
    Inventors: Roger S. Countryman, Sunil Khatri
  • Patent number: 4982250
    Abstract: A floating gate device has a control gate and a floating gate. The floating gate is for charging to set a logic state therein. Moisture is a problem in causing the floating gate to either lose its charge or becoming charged to the wrong state. A thin nitride layer deposited over the control gate and along the sides of the floating gate and control gate as a moisture barrier. This nitride layer is sufficiently thin so as to provide only insignificant attenuation of ultra-violet light used to neutralize the charge state of the floating gate. This nitride layer is not used as a passivation layer so that the desirable phoshosilicate glass (PSG) can be used for passivation.
    Type: Grant
    Filed: January 4, 1989
    Date of Patent: January 1, 1991
    Assignee: Motorola, Inc.
    Inventors: Peter N. Manos, II, Roger S. Countryman, Jr.
  • Patent number: 4573144
    Abstract: A fusible link having a programmable floating gate transistor in a first active region uses an extension of the floating gate to a second active region to provide electrons to the floating gate by the method of tunneling or the method of hot electron injection to avoid applying high voltage to the output terminals of the programmable floating gate transistor.
    Type: Grant
    Filed: September 30, 1982
    Date of Patent: February 25, 1986
    Assignee: Motorola, Inc.
    Inventor: Roger S. Countryman, Jr.
  • Patent number: 4532611
    Abstract: A circuit is provided in MOS technology which replaces a defective row of memory cells with a redundant row of memory cells in response to the address of the defective row and an implementation signal. The defective row is disabled by a floating gate fusible link which responds to the output of the decoder of the defective row as driven by the address thereof and to the implementation signal. The redundant row is implemented by floating gate fusible links which disable the inputs of the decoder of the redundant row which correspond to complements of the address in response to the address and the implementation signal. The implemented redundant row then receives address signals without any additional propagation delays.
    Type: Grant
    Filed: November 1, 1982
    Date of Patent: July 30, 1985
    Assignee: Motorola, Inc.
    Inventor: Roger S. Countryman, Jr.
  • Patent number: 4465973
    Abstract: In a memory array of capacitive storage cells having first and second polysilicon layers, an accelerated test for defects in insulating layers between substrate and first polysilicon and between first and second polysilicon is made possible by providing a probe pad which is connected to the connection between the first polysilicon and a resistor. The test is further facilitated by replacing the normally diffused resistor by a polysilicon resistor.
    Type: Grant
    Filed: May 17, 1982
    Date of Patent: August 14, 1984
    Assignee: Motorola, Inc.
    Inventor: Roger S. Countryman, Jr.
  • Patent number: 4380866
    Abstract: A process is disclosed for fabricating a MOS ROM which allows programming of the ROM late in the process sequence. A conventional silicon gate process is used to fabricate the devices up through the step of patterning the polycrystalline silicon gate electrode. Selected devices in the array are then programmed to an off-state by fabricatng those devices with either the source or drain region offset from the gate electrode. This is accomplished by a programming mask which, together with the gate electrode, provides selective location of the source or drain regions. Devices having an offset source or drain are off-state devices, while those having a normal source and drain function conventionally and conduct when a read voltage is applied.
    Type: Grant
    Filed: May 4, 1981
    Date of Patent: April 26, 1983
    Assignee: Motorola, Inc.
    Inventors: Roger S. Countryman, Jr., Paul T. Lin