Patents by Inventor Roger Thomas Baker

Roger Thomas Baker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4112510
    Abstract: A dynamic memory cell with automatic refreshing is described which requires only three insulated gate field effect transistors (IGFETs). Binary datum is stored in the cell by maintaining the gate of the first IGFET high for a one and low for a zero. The second IFGET is used for cell selection in the read and write operations, and is in series with the first transistor. The third IGFET has one gate electrode, but the channel region of this transistor has two regions, and the surface potential vs. gate voltage characteristics of these two regions differ. Regardless of the datum stored in the cell, pulsing the gate of this third transistor refreshes the memory cell.
    Type: Grant
    Filed: May 25, 1977
    Date of Patent: September 5, 1978
    Inventor: Roger Thomas Baker
  • Patent number: 4092736
    Abstract: A semiconductor random access memory is described in which the datum stored in one memory cell can be recalled without having to recall, temporarily store, and then re-enter the data stored in a column of memory cells. Datum can also be entered into one memory cell without having to recall and subsequently re-enter the data in a column of memory cells. During the recall and enter processes, only one of the normally off sense amps needs to be powered up. Compared to prior art one-transistor memories, this memory consumes less power and has a faster write cycle.
    Type: Grant
    Filed: July 6, 1976
    Date of Patent: May 30, 1978
    Inventor: Roger Thomas Baker
  • Patent number: 4062001
    Abstract: A dynamic semiconductor memory cell which can be used in content addressable or associative memories is described. In the memory cell, a one is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a first storage electrode, and a zero is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a second storage electrode. The match zero operation is performed by extracting some of any of the minority carriers stored beneath the first storage electrode, which induces a relatively small potential change on that electrode if a zero is stored in the memory cell and induces a relatively large potential change on that electrode if a one is stored therein. Similarly, the match one operation is performed by interrogating the minority carriers stored in the potential well beneath the second storage electrode.
    Type: Grant
    Filed: August 12, 1976
    Date of Patent: December 6, 1977
    Inventor: Roger Thomas Baker