Abstract: An improved memory cell circuit in which the collector of the "ON" transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for limiting the voltage between a first node in the word line circuit and the collector of the conducting transistor to a first level, while limiting the voltage between the first node and the collector of the nonconducting transistor to a second, lower level.In one embodiment, clamping transistors have their emitters coupled to the collectors of the memory cell transistors and their bases coupled to the word line. A common resistor couples the load resistors of a plurality of memory cells to the word line.In a second embodiment, the common resistor couples the bases of the clamping transistors to an intermediate node in a Darlington driver for the word line.

Abstract: An apparatus for reducing the write recovery time of a memory during a write operation is responsive to the detection of a write enable signal for causing the data being written into a selected memory cell to be immediately coupled out on the memory's corresponding output data line independent of the speed at which the data is actually written into the memory cell. The state of a cache memory element is set to reflect this data state such that when the write enable signal goes off, the cache memory element maintains the present state of said output data line. The cache memory element is overridden as the corresponding memory cell reaches a steady state condition at the end of the write operation.

Abstract: Circuitry for presetting a bipolar random access memory includes switching transistors, responsive to an applied memory preset signal, for opening the circuit between the memory word lines and their respective current sources, for applying a positive voltage to the bottom word lines, for breaking the circuitry between bit line clamping circuits and their respective power sources, and for grounding the bit line pairs to drain all current from the bit line circuits. The preset circuitry also includes read/write control transistors coupled between each bit line and a V.sub.cc source for steering the set of the memory cells upon removal of the preset signal.

Abstract: An adaptive word line pull-down circuit steers a pull-down current only to the word being pulled down and only for the time when that word is being pulled down. The time that it takes for the bottom word line to fall controls how long the pull-down current is steered to the falling word.