Patents by Inventor Roger W. Cheek
Roger W. Cheek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120181627Abstract: A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm3, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm3. The altered halo region is in direct contact with the altered extension region.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Jeffrey B. Johnson, Chung H. Lam, Beth A. Rainey, Michael J. Zierak
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Publication number: 20120181628Abstract: A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm3, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm3. The altered halo region is in direct contact with the altered extension region.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Jeffrey B. Johnson, Chung H. Lam, Beth A. Rainey, Michael J. Zierak
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Publication number: 20120129313Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
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Publication number: 20120126194Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
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Publication number: 20120112154Abstract: A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott
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Patent number: 8138056Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.Type: GrantFiled: July 3, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Bipin Rajendran, Alejandro G. Schrott, Yu Zhu
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Patent number: 8115186Abstract: A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.Type: GrantFiled: July 7, 2009Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric Andrew Joseph, Chung Hon Lam, Hsiang-Lan Lung, Alejandro Gabriel Schrott
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Patent number: 8105859Abstract: A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.Type: GrantFiled: September 9, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott
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Publication number: 20110228600Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 8023345Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: GrantFiled: February 24, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Publication number: 20110186800Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.Type: ApplicationFiled: April 11, 2011Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek
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Patent number: 7960203Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.Type: GrantFiled: January 29, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek
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Publication number: 20110057162Abstract: A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.Type: ApplicationFiled: September 9, 2009Publication date: March 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott
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Patent number: 7901980Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode.Type: GrantFiled: August 7, 2009Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Roger W. Cheek, Chung H. Lam, Stephen M. Rossnagel, Alejandro G. Schrott
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Publication number: 20110001111Abstract: A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.Type: ApplicationFiled: July 3, 2009Publication date: January 6, 2011Applicant: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Blpin Rajendran, Alejandro G. Schrott, Yu Zhu
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Patent number: 7851323Abstract: The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.Type: GrantFiled: July 10, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Eric A. Joseph, Chung H. Lam, Alejandro G. Schrott, Gerhard Ingmar Meijer
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Publication number: 20100299297Abstract: A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.Type: ApplicationFiled: May 21, 2009Publication date: November 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Joseph Breitwisch, Roger W. Cheek, Chung Hon Lam, Dharmendra Shantilal Modha, Bipin Rajendran
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Publication number: 20100214829Abstract: Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.Type: ApplicationFiled: February 24, 2009Publication date: August 26, 2010Applicant: International Business Machines CorporationInventors: Matthew J. Breitwisch, Roger W. Cheek, Stefanie R. Chiras, Ibrahim M. Elfadel, Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano, Thomas Mittelholzer, Mayank Sharma
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Patent number: 7682945Abstract: The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.Type: GrantFiled: February 4, 2008Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Chung H. Lam, Matthew J. Breitwisch, Roger W. Cheek, Alejandro G. Schrott, Matthew D. Moon
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Publication number: 20090298223Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode.Type: ApplicationFiled: August 7, 2009Publication date: December 3, 2009Applicant: International Business Machines CorporationInventors: Roger W. Cheek, Chung H. Lam, Stephen M. Rossnagel, Alejandro G. Schrott