Abstract: Disclosed are a system and method of replacing data in cache ways of a cache memory array. If one or more cache ways are locked from replacement, a cache way may be selected from among the unlocked cache ways based upon a pseudo random selection scheme.

Abstract: Disclosed are a system and method of replacing data in cache ways of a cache memory array. If one or more cache ways are locked from replacement, a cache way may be selected from among the unlocked cache ways based upon a pseudo random selection scheme.

Abstract: A method and system for cache replacement among configurable cache sets. In one embodiment, the present invention identifies a cache location corresponding to uncached data received from main memory and determines a data type for the uncached data. The present invention then examines the cache location in at least one of the configurable cache sets which is configured for the data type of the uncached data. Provided that the cache location of at least one of the configurable cache sets is not occupied by valid data and that the same configurable cache set is configured for the data type of the uncached data, the present invention stores the uncached data into that configurable cache set at the cache location without displacing valid data therein.

Abstract: A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct.

Abstract: A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct.