Patents by Inventor Roger White
Roger White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7694262Abstract: A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.Type: GrantFiled: October 16, 2007Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Timothy Wayne Kemerer, Robert Mark Rassel, Steven M. Shank, Francis Roger White
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Publication number: 20100052026Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.Type: ApplicationFiled: August 28, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Edward Barth, JR., Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White
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Publication number: 20090100388Abstract: A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.Type: ApplicationFiled: October 16, 2007Publication date: April 16, 2009Inventors: Timothy Wayne Kemerer, Robert Mark Rassel, Steven M. Shank, Francis Roger White
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Publication number: 20080315274Abstract: A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Inventors: Timothy Wayne Kemerer, Robert Mark Rassel, Steven M. Shank, Francis Roger White
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Patent number: 7337713Abstract: A bale wrapping control system that enables several custom bale wrapping patterns which more effectively wrap and maintain the integrity of bales formed in a round baler. The bale wrapping control system controls operation of a dispensing arm which dispenses twine or other bale wrapping material. The dispensing arm is moveable between a start position where an end of the dispensing arm is closest to the bale, a left edge position where the end of the dispensing arm is near a left edge of the bale, a right edge position where the end of the dispensing arm is near a right edge of the bale, and a cutoff or home position where the end of the dispensing arm passes a cutting mechanism. The bale wrapping control system includes a baler controller for controlling movement of the dispensing arm and a user interface for receiving operating instructions from an operator of the baler and for controlling certain functions of the baler controller in response to the operating instructions.Type: GrantFiled: August 1, 2006Date of Patent: March 4, 2008Assignee: AGCO CorporationInventors: Brian D. Olander, Maynard M. Herron, Charlie O. James, Robert J. Waggoner, Roger A. White
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Publication number: 20080034984Abstract: A bale wrapping control system that enables several custom bale wrapping patterns which more effectively wrap and maintain the integrity of bales formed in a round baler. The bale wrapping control system controls operation of a dispensing arm which dispenses twine or other bale wrapping material. The dispensing arm is moveable between a start position where an end of the dispensing arm is closest to the bale, a left edge position where the end of the dispensing arm is near a left edge of the bale, a right edge position where the end of the dispensing arm is near a right edge of the bale, and a cutoff or home position where the end of the dispensing arm passes a cutting mechanism. The bale wrapping control system includes a baler controller for controlling movement of the dispensing arm and a user interface for receiving operating instructions from an operator of the baler and for controlling certain functions of the baler controller in response to the operating instructions.Type: ApplicationFiled: August 1, 2006Publication date: February 14, 2008Inventors: Brian J. Olander, Maynard M. Herron, Charlie O. James, Robert J. Waggoner, Roger A. White
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Publication number: 20060264964Abstract: The invention relates, according to one embodiment, to a graft syringe assembly for delivering bone graft material is disclosed. The graft syringe assembly comprises a syringe subassembly including a syringe barrel having an inner chamber adapted for receiving bone graft material, a plunger adapted for expelling bone graft material from the inner chamber, the plunger slidably received within the inner chamber, and a syringe adapter coupled to the syringe barrel. The graft syringe assembly further comprises a connection subassembly coupled to the syringe adapter, and a delivery tube subassembly coupled to the connection subassembly, wherein the connection subassembly is configured to allow the delivery tube subassembly to rotate relative to the syringe subassembly.Type: ApplicationFiled: May 19, 2005Publication date: November 23, 2006Inventors: Jeffrey Scifert, Stephen Mariano, Richard Wisdom, Gary Whipple, A. Boccuti, Roger White, Thomas Washburn
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Publication number: 20060121469Abstract: Screening methods for identifying compounds that are useful as contraceptives are provided. In particular, the compounds inhibit the interaction between steroidogenic factor 1 (SF-1) and nuclear receptor interacting protein (Nrip1) or the up-regulate SF-1 expression.Type: ApplicationFiled: July 4, 2003Publication date: June 8, 2006Inventors: George Parker, Roger White, Goran Leonardsson
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Patent number: 6680259Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.Type: GrantFiled: April 14, 2003Date of Patent: January 20, 2004Assignee: International Business Machines CorporationInventors: Chung Hon Lam, Eric Seung Lee, Francis Roger White
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Publication number: 20030207586Abstract: A method for reactive ion etching of Si02 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.Type: ApplicationFiled: April 14, 2003Publication date: November 6, 2003Applicant: International Business Machines CorporationInventors: Chung Hon Lam, Eric Seung Lee, Francis Roger White
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Patent number: 6548418Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.Type: GrantFiled: May 30, 2002Date of Patent: April 15, 2003Assignee: International Business Machines CorporationInventors: Chung Hon Lam, Eric Seung Lee, Francis Roger White
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Publication number: 20030058675Abstract: An SRAM memory cell made with increased stability using SOI technology is provided. Increased stability occurs because of raising the threshold voltage of the transfer nfets connected to the word line. Preferably the increase of threshold voltage is achieved using boron ion implantation.Type: ApplicationFiled: September 25, 2001Publication date: March 27, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Gus Aipperspach, Andres Bryant, Todd Alan Christensen, Dennis T. Cox, Jerome Brett Lasky, John Edward Sheets, Francis Roger White
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Publication number: 20020145179Abstract: 59 A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.Type: ApplicationFiled: May 30, 2002Publication date: October 10, 2002Applicant: International Business Machines CorporationInventors: Chung Hon Lam, Eric Seung Lee, Francis Roger White
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Patent number: 6446813Abstract: From one aspect the invention is a method of classifying waste materials comprising arranging two sieve screens, each having an inlet end and an outlet end, one above the other to define a space there between, arranging the upper screen, to be of coarser mesh size than the lower screen, supplying waste material to be classified to the inlet end of the upper screen, vibrating the screens, and blowing air between the screens from the inlet end and towards the outlet end whereby the waste material being blown away from the outlet ends of the screens, and large heavy material falling under gravity from the outlet end of the upper screen, and separately collecting the separated waste material fractions. From another aspect the invention is an apparatus for carrying out the method described above.Type: GrantFiled: November 23, 1999Date of Patent: September 10, 2002Inventor: Roger White
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Patent number: 6420777Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.Type: GrantFiled: February 26, 1998Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Chung Hon Lam, Eric Seung Lee, Francis Roger White
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Publication number: 20010013638Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.Type: ApplicationFiled: February 26, 1998Publication date: August 16, 2001Inventors: CHUNG HON LAM, ERIC SEUNG LEE, FRANCIS ROGER WHITE
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Patent number: 6174763Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors (“FETs”) buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed, A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.Type: GrantFiled: January 6, 1997Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Kenneth Edward Beilstein, Jr., Claude Louis Bertin, John Edward Cronin, Francis Roger White
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Patent number: 6140171Abstract: A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.Type: GrantFiled: January 20, 1999Date of Patent: October 31, 2000Assignee: International Business Machines CorporationInventors: Archibald John Allen, Jerome Brett Lasky, Randy William Mann, John Joseph Pekarik, Jed Hickory Rankin, Edward William Sengle, Francis Roger White
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Patent number: 6022766Abstract: An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.Type: GrantFiled: February 10, 1997Date of Patent: February 8, 2000Assignee: International Business Machines, Inc.Inventors: Bomy Able Chen, Subhash Balakrishna Kulkarni, Jerome Brett Lasky, Randy William Mann, Edward Joseph Nowak, Werner Alois Rausch, Francis Roger White
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Patent number: 5675185Abstract: An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.Type: GrantFiled: September 29, 1995Date of Patent: October 7, 1997Assignee: International Business Machines CorporationInventors: Bomy Able Chen, Subhash Balakrishna Kulkarni, Jerome Bret Lasky, Randy William Mann, Edward Joseph Nowak, Werner Alois Rausch, Francis Roger White