Patents by Inventor Roger Yacobucci

Roger Yacobucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)
    Patent number: 7565592
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: July 21, 2009
    Assignee: LSI Corporation
    Inventor: Roger Yacobucci
  • Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)
    Patent number: 7430700
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 30, 2008
    Assignee: LSI Logic Corporation
    Inventor: Roger Yacobucci
  • FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
    Publication number: 20080162070
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a slown good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 3, 2008
    Applicant: LSI LOGIC CORPORATION
    Inventor: Roger Yacobucci
  • Failure Analysis and Testing of Semi-conductor Devices using Intelligent Software on Automated Test Equipment (ATE)
    Publication number: 20070179745
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Application
    Filed: February 1, 2007
    Publication date: August 2, 2007
    Applicant: LSI LOGIC CORPORATION
    Inventor: Roger Yacobucci
  • Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)
    Patent number: 7203877
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventor: Roger Yacobucci
  • Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)
    Publication number: 20060150041
    Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.
    Type: Application
    Filed: January 4, 2005
    Publication date: July 6, 2006
    Inventor: Roger Yacobucci