Abstract: Content comprising a sequence of original frames at a first frame rate is up-converted to a second, higher, frame rate. Intermediate frames are calculated for temporal positions spaced between temporal positions of the original frames. An output sequence at the second frame rate comprises a repeating pattern of frames and, within each repetition of the pattern, there is: at least one original frame; at least one intermediate frame which is repeated; and at least one frame which is not repeated. The method is suitable for applications where an up-conversion factor is required in the frame rate, such as an up-conversion factor of five to up-convert from the 24 Hz frame rate used for film-based content to the 120 Hz frame rate used by displays. The output sequence can use all of the original frames to reduce detail flicker.

Abstract: Content comprising a sequence of original frames at a first frame rate is up-converted to a second, higher, frame rate. Intermediate frames are calculated for temporal positions spaced between temporal positions of the original frames. An output sequence at the second frame rate comprises a repeating pattern of frames and, within each repetition of the pattern, there is: at least one original frame; at least one intermediate frame which is repeated; and at least one frame which is not repeated. The method is suitable for applications where an up-conversion factor is required in the frame rate, such as an up-conversion factor of five to up-convert from the 24 Hz frame rate used for film-based content to the 120 Hz frame rate used by displays. The output sequence can use all of the original frames to reduce detail flicker.

Abstract: Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the instructions contained in the instruction cache prior to execution of the ISR are overwritten by the ISRs instructions. To reduce trashing of the instruction cache memory, the instruction cache is dynamically partitioned into a first memory portion and a second memory portion during execution. The first memory portion is for storing instructions of the current instruction stream, and the second memory portion is for storing instructions of the ISR. Thus, the ISR only affects the second memory portion and leaves instruction data stored within the first memory portion intact. This partitioning of the instruction cache reduces processor fetch operations as well as reduces power consumption of the instruction cache memory.

Abstract: Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream (301) they interrupt; it is known as “instruction cache trashing,” since the instructions contained in the instruction cache (102) prior to execution of the ISR (302) are overwritten by the ISRs instructions. To reduce trashing of the instruction cache memory, the instruction cache is dynamically partitioned into a first memory portion (501a) and a second memory portion (501b) during execution. The first memory portion (501a) is for storing instructions of the current instruction stream (301), and the second memory portion (501b) is for storing instructions of the ISR (302). Thus, the ISR (302) only affects the second memory portion (501b) and leaves instruction data stored within the first memory portion (501a) intact. This partitioning of the instruction cache (102) reduces processor fetch operations as well as reduces power consumption of the instruction cache memory (102).