Patents by Inventor Rohan Babu NAGABHIRAVA

Rohan Babu NAGABHIRAVA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144965
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprises a first shield, a BiSb layer disposed over the first shield (S1), a free layer (FL) disposed over the BiSb layer, and a second shield (S2) disposed over the FL. The S1, the FL, and the S2 are disposed at a media facing surface (MFS). The BiSb layer is recessed from the MFS a first distance of about 5 nm to about 20 nm. The FL has a length greater than the first distance. A notch and/or an insulation layer is disposed adjacent to the BiSb layer at the MFS. Current may be configured to flow vertically through the S2 to the FL, and horizontally from the FL to the BiSb layer. Current may be configured to flow vertically through the S2 to the S1.
    Type: Application
    Filed: July 31, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Rohan Babu NAGABHIRAVA, Xiaoyong LIU, Brian R. YORK, Cherngye HWANG, Son T. LE, Randy G. SIMMONS, Kuok San HO, Hisashi TAKANO
  • Publication number: 20240144960
    Abstract: The present disclosure generally relates to a two dimensional magnetic recording (TDMR) spin-orbit torque (SOT) read head comprising bismuth antimony (BiSb) layers. The read head comprises a lower reader comprising a first SOT stack and an upper reader comprising a second SOT stack. The first SOT stack and the second SOT stack each individually comprise a BiSb layer recessed from a media facing surface (MFS) and a free layer exposed at the MFS. The BiSb layers of each SOT stack are recessed from the MFS a distance of about 5 nm to about 20 nm, the distance being less than a length of the free layers. In one embodiment, the lower reader and the upper reader share a current path. In another embodiment, the lower reader and the upper reader have separate current paths.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Rohan Babu NAGABHIRAVA, Xiaoyong LIU, Brian R. YORK, Son T. LE, Cherngye HWANG, Kuok San HO, Hisashi TAKANO