Patents by Inventor Rohan Braithwaite

Rohan Braithwaite has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitor structure with an extended dielectric layer and method of forming a capacitor structure
    Patent number: 10418438
    Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 17, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Randy Yach, Rohan Braithwaite
  • Capacitor Structure With An Extended Dielectric Layer And Method Of Forming A Capacitor Structure
    Publication number: 20180226469
    Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 9, 2018
    Applicant: Microchip Technology Incorporated
    Inventors: Randy Yach, Rohan Braithwaite
  • ESD-protection circuit for integrated circuit device
    Patent number: 9607978
    Abstract: A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 28, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Philippe Deval, Marija Fernandez, Patrick Besseux, Rohan Braithwaite
  • Multiple well drain engineering for HV MOS devices
    Patent number: 8962397
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite
  • ESD-Protection Circuit for Integrated Circuit Device
    Publication number: 20140210007
    Abstract: A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Inventors: Philippe Deval, Marija Fernandez, Patrick Besseux, Rohan Braithwaite
  • MULTIPLE WELL DRAIN ENGINEERING FOR HV MOS DEVICES
    Publication number: 20130026545
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 31, 2013
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite