Patents by Inventor Rohan Dhekane

Rohan Dhekane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10832789
    Abstract: Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die, the programming operation including populating a transfer data latch with a first set of data and transferring the data to a first data latch, populating the transfer data latch with a second set of data and transferring the data to second data latch, arranging the first and second data sets in a suitable format of the multi-state block, and writing the data sets to the multi-state block; prior to populating the transfer data latch with the second data set, performing a program suspend and read operation thereby populating the transfer data latch with read data; and comparing the read data to the data contained in the first data latch and, if the comparison results in a match, identifying the subject die as faulty.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 10, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mahim Gupta, Rohan Dhekane, Aaron Lee
  • Patent number: 10770158
    Abstract: Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mahim Gupta, Rohit Sehgal, Rohan Dhekane, Niles Yang, Aaron Lee