Abstract: A central system coupled to a subsystem receives a fault indication associated with a fault in one or more circuits of the subsystem from a local fault collection and control (FCCS) of the subsystem when a software recovery of the fault fails. Based on the received fault indication, the local FCCS and a central FCCS of a central system is masked from additional fault indications from the one or more circuits. The central system then signals the reset of the one or more circuits of the subsystem after the masking of the additional fault indications, wherein the one or more circuits is reset based on the signaling and the additional faults are masked from one or more of the local FCCS and central FCCS during the reset.

Abstract: A central system coupled to a subsystem receives a fault indication associated with a fault in one or more circuits of the subsystem from a local fault collection and control (FCCS) of the subsystem when a software recovery of the fault fails. Based on the received fault indication, the local FCCS and a central FCCS of a central system is masked from additional fault indications from the one or more circuits. The central system then signals the reset of the one or more circuits of the subsystem after the masking of the additional fault indications, wherein the one or more circuits is reset based on the signaling and the additional faults are masked from one or more of the local FCCS and central FCCS during the reset.

Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.