Abstract: Disclosed herein is a device including a first voltage rail and a second voltage rail configured to provide a first voltage. A current source component is conductively coupled to the first voltage rail and the second voltage rail and is configured to provide a first current. A voltage translator is conductively coupled to the second voltage rail and the current source component and is configured to invert the first voltage to a second voltage and provide an output signal including the first current and the second voltage.

Abstract: A semiconductor device includes a cell transistor coupled to a bitline, a bias transistor coupled to the bitline and to a bias node, and a clamp transistor coupled between the bitline and a clamp node. A memory circuit includes an array of memory cell transistors coupled to respective bitlines, bias transistors having a source, a drain, and a gate, the source of each bias transistor coupled to a respective one of the bitlines, a bias node coupled to the gates of the bias transistors, a current source having first and second terminals, the first terminal coupled to the bias node, and the second terminal coupled to a reference node, and clamp transistors, each having a source, a drain, and a gate, the gate and source of each clamp transistor coupled to a respective one of the bitlines, and the drain of each clamp transistor coupled to a clamp node.

Abstract: Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

Abstract: A pulse generator circuit includes a charge pump having a charge pump output. A voltage divider is coupled to the charge pump output. The voltage divider has a voltage divider output. An error amplifier has a first error amplifier input and a second error amplifier input. The first error amplifier input is coupled to the voltage divider output. A dependent current source circuit has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. The dependent current source is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.

Abstract: A pulse generator circuit includes a charge pump having a charge pump output. A voltage divider is coupled to the charge pump output. The voltage divider has a voltage divider output. An error amplifier has a first error amplifier input and a second error amplifier input. The first error amplifier input is coupled to the voltage divider output. A dependent current source circuit has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. The dependent current source is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.

Abstract: A pulse generator circuit includes a charge pump having a charge pump output. A voltage divider is coupled to the charge pump output. The voltage divider has a voltage divider output. An error amplifier has a first error amplifier input and a second error amplifier input. The first error amplifier input is coupled to the voltage divider output. A dependent current source circuit has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. The dependent current source is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.

Abstract: Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

Abstract: Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.

Abstract: A charge pump circuit includes input and output charge pump stages. Each charge pump stage includes a respective voltage input, a respective voltage output, a respective first clock input and a respective second clock input. The voltage input of the input charge pump stage is coupled to a voltage supply terminal. The voltage output of the output charge pump stage is coupled to an output of the charge pump circuit. A clock driver circuit includes a first clock output, a second clock output, a first bias input and a second bias input. The first clock output is coupled to the first clock inputs, and the second clock output is coupled to the second clock inputs. A body bias circuit includes first and second bias outputs. The first bias output is coupled to the first bias input, and the second bias output is coupled to the second bias input.

Abstract: A charge pump circuit includes input and output charge pump stages. Each charge pump stage includes a respective voltage input, a respective voltage output, a respective first clock input and a respective second clock input. The voltage input of the input charge pump stage is coupled to a voltage supply terminal. The voltage output of the output charge pump stage is coupled to an output of the charge pump circuit. A clock driver circuit includes a first clock output, a second clock output, a first bias input and a second bias input. The first clock output is coupled to the first clock inputs, and the second clock output is coupled to the second clock inputs. A body bias circuit includes first and second bias outputs. The first bias output is coupled to the first bias input, and the second bias output is coupled to the second bias input.

Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.