Abstract: A packet-based processing system suitable for various applications, such as for a base station or a terminal in a wireless communication system, is described. The packet-based processing system may include multiple processing modules and at least one transport module. The processing modules may send packets to one another via a common packet interface and may operate asynchronously. The transport module(s) may forward the packets sent by the processing modules and may operate asynchronously with respect to the processing modules. Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit. Each processing module may support at least one service. Each packet may include a header and a payload. The header may include a source service address for a source service sending the packet and a destination service address for a recipient service receiving the packet.

Abstract: A receiver operates to AGC a multi-carrier signal through a corresponding number of inner loops and an outer loop AGC processes. A first number of bits for representing the multi-carrier signal with a limited amount of interference is determined through a calibration mode process. The first number of bits provides for quantization of the multi-carrier signal at an outer loop AGC to a maximum quantization level. After the received signal power estimate is reached a predetermined “ON” threshold, the outer loop AGC is operated at a second number of bits higher than the first number of bits to allow a quantization of possible interference in accordance with a difference of the first and second number of bits. The outer loop AGC switches back to use the first number of bits when the received signal power estimate falls below a predetermined “OFF” threshold.

Abstract: A packet-based processing system suitable for various applications, such as for a base station or a terminal in a wireless communication system, is described. The packet-based processing system may include multiple processing modules and at least one transport module. The processing modules may send packets to one another via a common packet interface and may operate asynchronously. The transport module(s) may forward the packets sent by the processing modules and may operate asynchronously with respect to the processing modules. Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit. Each processing module may support at least one service. Each packet may include a header and a payload. The header may include a source service address for a source service sending the packet and a destination service address for a recipient service receiving the packet.

Abstract: A receiver operates to AGC a multi-carrier signal through a corresponding number of inner loops and an outer loop AGC processes. A first number of bits for representing the multi-carrier signal with a limited amount of interference is determined through a calibration mode process. The first number of bits provides for quantization of the multi-carrier signal at an outer loop AGC to a maximum quantization level. After the received signal power estimate is reached a predetermined “ON” threshold, the outer loop AGC is operated at a second number of bits higher than the first number of bits to allow a quantization of possible interference in accordance with a difference of the first and second number of bits. The outer loop AGC switches back to use the first number of bits when the received signal power estimate falls below a predetermined “OFF” threshold.