Patents by Inventor Rohan U. Mandrekar
Rohan U. Mandrekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088032Abstract: Microelectronic modules are described. In an embodiment, a microelectronic module includes a module substrate, a chip mounted onto the module substrate, and a semiconductor-based integrated passive device between the chip and the module substrate. The semiconductor-based integrated passive device may include an upper RDL stack-up with thicker wiring layers than a lower BEOL stack-up. The semiconductor-based integrated passive device may be further solder bonded or hybrid bonded with the chip.Type: ApplicationFiled: September 14, 2022Publication date: March 14, 2024Inventors: Vidhya Ramachandran, Chi Nung Ni, Chueh-An Hsieh, Rekha Govindaraj, Jun Zhai, Long Huang, Rohan U. Mandrekar, Saumya K. Gandhi, Zhuo Yan, Yizhang Yang, Saurabh P. Sinha, Antonietta Oliva
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Publication number: 20240063715Abstract: A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Alexander B. Uan-Zo-li, Shuai Jiang, Jamie L. Langlinais, Per H. Hammarlund, Hans L. Yeager, Victor Zyuban, Sung J. Kim, Wei Xu, Rohan U. Mandrekar, Sambasivan Narayan, Mohamed H. Abu-Rahma, Jaroslav Raszka, Robert O. Bruckner
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Patent number: 11076493Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.Type: GrantFiled: July 18, 2018Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Douglas A. Baska, Daniel M. Dreps, Rohan U. Mandrekar, Roger D. Weekly
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Patent number: 11069665Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.Type: GrantFiled: November 30, 2018Date of Patent: July 20, 2021Assignee: Apple Inc.Inventors: Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Mengzhi Pang, Rohan U. Mandrekar
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Publication number: 20200176427Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.Type: ApplicationFiled: November 30, 2018Publication date: June 4, 2020Inventors: Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Mengzhi Pang, Rohan U. Mandrekar
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Publication number: 20180352662Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.Type: ApplicationFiled: July 18, 2018Publication date: December 6, 2018Inventors: Douglas A. Baska, Daniel M. Dreps, Rohan U. Mandrekar, Roger D. Weekly
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Patent number: 10034393Abstract: Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.Type: GrantFiled: November 25, 2013Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Douglas A. Baska, Daniel M. Dreps, Rohan U. Mandrekar, Roger D. Weekly
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Patent number: 9972566Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.Type: GrantFiled: October 28, 2016Date of Patent: May 15, 2018Assignee: International Business Machines CorporationInventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Patent number: 9646925Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.Type: GrantFiled: August 12, 2015Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Patent number: 9600619Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.Type: GrantFiled: August 25, 2015Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Patent number: 9594865Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.Type: GrantFiled: May 20, 2015Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Publication number: 20170048967Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Patent number: 9543241Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.Type: GrantFiled: November 24, 2014Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Publication number: 20170004923Abstract: In one embodiment, a method includes positioning a first signal pad in a first layer of a printed circuit board and positioning a second signal pad in a second layer of the printed circuit board. The second signal pad is positioned to form an embedded capacitance between the first signal pad and the second signal pad. The embedded capacitance between the first signal pad and the second signal pad is configured to carry a signal between the first layer and the second layer absent a signal via.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U Mandrekar, Tingdong Zhou
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Publication number: 20160342724Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.Type: ApplicationFiled: August 25, 2015Publication date: November 24, 2016Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Publication number: 20160342723Abstract: One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.Type: ApplicationFiled: May 20, 2015Publication date: November 24, 2016Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Patent number: 9456506Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.Type: GrantFiled: December 20, 2013Date of Patent: September 27, 2016Assignee: International Business Machines CorporationInventors: John L. Colbert, Daniel M. Dreps, Paul M. Harvey, Rohan U. Mandrekar
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Patent number: 9445507Abstract: A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.Type: GrantFiled: June 5, 2015Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: John L. Colbert, Daniel M. Dreps, Paul M. Harvey, Rohan U. Mandrekar
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Publication number: 20160149611Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.Type: ApplicationFiled: August 12, 2015Publication date: May 26, 2016Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
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Publication number: 20160150638Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.Type: ApplicationFiled: November 24, 2014Publication date: May 26, 2016Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou