Patents by Inventor Rohit Bhadana

Rohit Bhadana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12086521
    Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: September 10, 2024
    Assignee: Xilinx, Inc.
    Inventors: Tharun Kumar Ksheerasagar, Rohit Bhadana, Hemant Kashyap, Pratyush Ranjan
  • Patent number: 11630935
    Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 18, 2023
    Assignee: Xilinx, Inc.
    Inventors: Amit Kasat, Tharun Kumar Ksheerasagar, Hemant Kashyap, Madhusudana Reddy, Rohit Bhadana
  • Publication number: 20230114858
    Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.
    Type: Application
    Filed: October 7, 2021
    Publication date: April 13, 2023
    Applicant: Xilinx, Inc.
    Inventors: Tharun Kumar Ksheerasagar, Rohit Bhadana, Hemant Kashyap, Pratyush Ranjan
  • Publication number: 20230113197
    Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 13, 2023
    Applicant: Xilinx, Inc.
    Inventors: Amit Kasat, Tharun Kumar Ksheerasagar, Hemant Kashyap, Madhusudana Reddy, Rohit Bhadana