Patents by Inventor Rohit Galatage

Rohit Galatage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10629428
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shariq Siddiqui, Han You, Xunyuan Zhang, Rohit Galatage, Roger A. Quon, Christopher J. Penny
  • Publication number: 20200035786
    Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Inventors: Ruilong Xie, Julien Frougier, Nigel G. Cave, Steven R. Soss, Daniel Chanemougame, Steven Bentley, Rohit Galatage, Bum Ki Moon
  • Patent number: 10446659
    Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Rohit Galatage, Puneet Harischandra Suvarna
  • Publication number: 20190279860
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Shariq SIDDIQUI, Han YOU, Xunyuan ZHANG, Rohit GALATAGE, Roger A. QUON, Christopher J. PENNY
  • Patent number: 10340146
    Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Shariq Siddiqui, Chung-Ju Yang
  • Patent number: 10332969
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Publication number: 20190115437
    Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 18, 2019
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Publication number: 20190115444
    Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven BENTLEY, Rohit GALATAGE, Puneet Harischandra Suvarna
  • Publication number: 20190019682
    Abstract: Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 17, 2019
    Inventors: Rohit Galatage, Shariq Siddiqui, Chung-Ju Yang
  • Patent number: 10141414
    Abstract: A gate electrode structure of a transistor element may be provided as a series connection of a negative capacitor portion and a floating electrode portion. When forming the negative capacitor portion, the value of the negative capacitance may be adjusted on the basis of two different mechanisms or manufacturing processes, thereby providing superior matching of the positive floating gate electrode portion and the negative capacitor portion. For example, the layer thickness of the ferroelectric material and the effective capacitive area of the dielectric material may be adjusted on the basis of independent manufacturing processes.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rohit Galatage, Steven Bentley, Puneet Harischandra Suvarna, Zoran Krivokapic
  • Patent number: 9577042
    Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven Bentley, Rohit Galatage
  • Publication number: 20170047404
    Abstract: The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material.
    Type: Application
    Filed: August 13, 2015
    Publication date: February 16, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Steven BENTLEY, Rohit GALATAGE
  • Patent number: 9484449
    Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Rohit Galatage, Hoon Kim
  • Publication number: 20160133716
    Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shariq Siddiqui, Bhagawan Sahu, Rohit Galatage, Hoon Kim
  • Publication number: 20160056253
    Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Rohit Galatage, Hoon Kim
  • Patent number: 9263541
    Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shariq Siddiqui, Bhagawan Sahu, Rohit Galatage, Hoon Kim
  • Publication number: 20150311308
    Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Shariq Siddiqui, Bhagawan Sahu, Rohit Galatage, Hoon Kim