Patents by Inventor Rohit Goel

Rohit Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11635465
    Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: April 25, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Rohit Goel, Anand Kumar Mishra, Rajnish Garg
  • Publication number: 20220137133
    Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.
    Type: Application
    Filed: October 18, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics International N.V.
    Inventors: Rohit GOEL, Anand Kumar MISHRA, Rajnish GARG
  • Patent number: 9491178
    Abstract: A computer-implemented method includes retrieving, by one or more processing devices and from one or more data repositories, user information; generating, based on the retrieved user information, a digital personal profile that is a composite of a set of pre-defined attributes; determining an aggregate strength of values of the set of pre-defined attributes in the digital personal profile; and generating, based on the determined aggregate strength, a digital security score that measures a level of online security of accessing resources over a computer network.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 8, 2016
    Assignee: FMR LLC
    Inventors: Lori Bubany, Christopher Eastman, Rohit Goel, Arun Varghese, Stephanie West
  • Publication number: 20160241561
    Abstract: A computer-implemented method includes retrieving, by one or more processing devices and from one or more data repositories, user information; generating, based on the retrieved user information, a digital personal profile that is a composite of a set of pre-defined attributes; determining an aggregate strength of values of the set of pre-defined attributes in the digital personal profile; and generating, based on the determined aggregate strength, a digital security score that measures a level of online security of accessing resources over a computer network.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Lori Bubany, Christopher Eastman, Rohit Goel, Arun Varghese, Stephanie West
  • Patent number: 7352169
    Abstract: Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Jais Abraham, Rohit Goel
  • Publication number: 20080001616
    Abstract: Testing the components of I/O paths in an integrated circuit at at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.
    Type: Application
    Filed: May 26, 2006
    Publication date: January 3, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jais ABRAHAM, Rohit GOEL