Patents by Inventor Rohit Goyal

Rohit Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200388166
    Abstract: Disclosed are methods and systems for predicting time varying loudness in a geographic region. Training data, including noise information, weather information, and traffic information is collected from a plurality of sensors located in a plurality of geographic regions. The information is collected during multiple time periods. The noise information includes time varying loudness. Static features of the geographic regions are also defined and included in the training data. The static and time varying dynamic features train a model. The model is used predict time varying loudness within a different region and at a time later than times the training data is collected. The predicted loudness levels are utilized, in some aspects, to determine a route for an aircraft.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 10, 2020
    Inventors: Alireza Rostamzadeh, Rohit Goyal, Ryan Cunningham, Jane Yen Hung, Stanley Swaintek
  • Publication number: 20200336484
    Abstract: Systems and methods include intercepting traffic on a mobile device based on a set of rules; determining whether a connection associated with the traffic is allowed based on a local map associated with an application; responsive to the connection being allowed or blocked based on the local map, one of forwarding the traffic associated with the connection when allowed and generating a block of the connection at the mobile device when blocked; and, responsive to the connection not having an entry in the local map, forwarding a request for the connection to a cloud-based system for processing therein. The cloud-based system is configured to allow or block the connection based on the connection not having an entry in the local map.
    Type: Application
    Filed: July 7, 2020
    Publication date: October 22, 2020
    Inventors: Vikas Mahajan, Rohit Goyal
  • Patent number: 10708233
    Abstract: Systems and methods of identifying and processing certificate pinned applications through a cloud based security system include monitoring traffic associated with a connection; developing a profile of an application associated with the traffic based on the monitoring, wherein the profile comprises whether or not the application is a certificate pinned application which requires a predefined set of criterion to be matched against an advertised certificate; and selectively performing SSL interception of the connection in the cloud based security system based on the profile. The monitoring can include monitoring handshake messages between a client and a server to determine a handshake status and a certificate status.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 7, 2020
    Assignee: Zscaler, Inc.
    Inventors: Rohit Goyal, Abhinav Bansal
  • Publication number: 20180288062
    Abstract: Systems and methods of identifying and processing certificate pinned applications through a cloud based security system include monitoring traffic associated with a connection; developing a profile of an application associated with the traffic based on the monitoring, wherein the profile comprises whether or not the application is a certificate pinned application which requires a predefined set of criterion to be matched against an advertised certificate; and selectively performing SSL interception of the connection in the cloud based security system based on the profile. The monitoring can include monitoring handshake messages between a client and a server to determine a handshake status and a certificate status.
    Type: Application
    Filed: May 25, 2017
    Publication date: October 4, 2018
    Inventors: Rohit GOYAL, Abhinav BANSAL
  • Patent number: 9947059
    Abstract: A system platform and associated methods are provided for implementing online reverse auctions in a social network platform (SNP). A fully-automated, live, reverse-auction based system is integrated into an SNP to enable buyers to initiate desired transactions and take advantage of a subscribers' network of friends, colleagues, co-workers, family members and connections by connecting buyers and sellers in a non-intrusive, targeted fashion. Sellers compete for buyers' business by providing dynamic, real-time seller-specific pricing while simultaneously optimizing the seller's target parameters such as price, inventory levels, profit, revenue and volume.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 17, 2018
    Inventors: Mukesh Chatter, Rohit Goyal, Priti Chatter, Shiao-bin Soong
  • Patent number: 9306576
    Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 5, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Naman Gupta, Gaurav Goyal, Rohit Goyal
  • Patent number: 9294099
    Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rohit Goyal, Deepak Kumar Behera, Naman Gupta
  • Publication number: 20150188546
    Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Rohit Goyal, Deepak Kumar Behera, Naman Gupta
  • Patent number: 9032009
    Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semicondutor, Inc.
    Inventors: Rohit Goyal, Amit Kumar Dey
  • Publication number: 20150023463
    Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 22, 2015
    Inventors: Naman Gupta, Gaurav Goyal, Rohit Goyal
  • Patent number: 8933731
    Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rohit Goyal, Amit Kumar Dey, Naman Gupta
  • Patent number: 8924245
    Abstract: A system for and method of automatic optimizing quantitative business objectives of sellers (advertisers) with synergistic pricing, promotions and advertisements, while simultaneously minimizing expenditure and discovery and optimizing allocation of advertising channels that optimize such objectives.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: December 30, 2014
    Inventors: Mukesh Chatter, Rohit Goyal, Shiao-bin Soong
  • Patent number: 8867694
    Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: October 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Naman Gupta, Gaurav Goyal, Rohit Goyal
  • Publication number: 20140253215
    Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.
    Type: Application
    Filed: November 11, 2013
    Publication date: September 11, 2014
    Inventors: Rohit Goyal, Amit Kumar Dey, Naman Gupta
  • Publication number: 20140253214
    Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Rohit Goyal, Amit Kumar Dey
  • Publication number: 20140244419
    Abstract: A system platform and associated methods are provided for implementing online reverse auctions in a social network platform (SNP). A fully-automated, live, reverse-auction based system is integrated into an SNP to enable buyers to initiate desired transactions and take advantage of a subscribers' network of friends, colleagues, co-workers, family members and connections by connecting buyers and sellers in a non-intrusive, targeted fashion. Sellers compete for buyers' business by providing dynamic, real-time seller-specific pricing while simultaneously optimizing the seller's target parameters such as price, inventory levels, profit, revenue and volume.
    Type: Application
    Filed: May 5, 2014
    Publication date: August 28, 2014
    Applicant: Peak Silver Advisors, LLC
    Inventors: Mukesh Chatter, Rohit Goyal, Priti Chatter, Shiao-bin Soong
  • Publication number: 20140244420
    Abstract: A system platform and associated methods are provided for implementing online reverse auctions in a social network platform (SNP). A fully-automated, live, reverse-auction based system is integrated into an SNP to enable buyers to initiate desired transactions and take advantage of a subscribers' network of friends, colleagues, co-workers, family members and connections by connecting buyers and sellers in a non-intrusive, targeted fashion. Sellers compete for buyers' business by providing dynamic, real-time seller-specific pricing while simultaneously optimizing the seller's target parameters such as price, inventory levels, profit, revenue and volume.
    Type: Application
    Filed: May 5, 2014
    Publication date: August 28, 2014
    Applicant: Peak Silver Advisors, LLC
    Inventors: Mukesh Chatter, Rohit Goyal, Priti Chatter, Shiao-bin Soong
  • Publication number: 20140222589
    Abstract: A system for and method of automatic optimizing quantitative business objectives of sellers (advertisers) with synergistic pricing, promotions and advertisements, while simultaneously minimizing expenditure and discovery and optimizing allocation of advertising channels that optimize such objectives.
    Type: Application
    Filed: April 8, 2014
    Publication date: August 7, 2014
    Applicant: Peak Silver Advisors, LLC
    Inventors: Mukesh Chatter, Rohit Goyal, Shiao-bin Soong
  • Publication number: 20140222590
    Abstract: A system for and method of automatic optimizing quantitative business objectives of sellers (advertisers) with synergistic pricing, promotions and advertisements, while simultaneously minimizing expenditure and discovery and optimizing allocation of advertising channels that optimize such objectives.
    Type: Application
    Filed: April 8, 2014
    Publication date: August 7, 2014
    Applicant: Peak Silver Advisors, LLC
    Inventors: Mukesh Chatter, Rohit Goyal, Shiao-bin Soong
  • Patent number: 8781875
    Abstract: An Internet system for and method of automatic optimizing quantitative business objectives of sellers (advertisers) with synergistic pricing, promotions and advertisements, while simultaneously minimizing expenditure and discovery and optimizing allocation of advertising channels that optimize such objectives.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 15, 2014
    Inventors: Mukesh Chatter, Rohit Goyal, Shiao-bin Soong