Patents by Inventor Rohit Grover

Rohit Grover has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971267
    Abstract: In some examples, user journey carbon footprint reduction may include generating, for a vehicle associated with a user, a carbon emission quota for user journey carbon footprint reduction. A predicted journey carbon emissions may be generated for the vehicle for a specified journey. Based on collaborative filtering, at least one goal-based and conditions-based recommendation may be generated for the user of the vehicle for the specified journey for the user journey carbon footprint reduction. Based on a user behavior model, a user-interface display may be generated for the specified journey for the user journey carbon footprint reduction. Further, based on the user behavior model, and real-time monitoring of the user and the vehicle, a real-time update of the user-interface display may be generated for the specified journey for the user journey carbon footprint reduction.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: April 30, 2024
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Rohit Mehra, Vibhu Saujanya Sharma, Dimple Walia, Prerna Khurana, Prasad Venkata Sai Banda, Rahul Grover, Sukanta Paul, Sunil Maggu
  • Publication number: 20220415877
    Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Benjamin Orr, Rohit Grover, Nathan Jack, Nicholas Thomson, Rui Ma, Ayan Kar, Kalyan Kolluru
  • Patent number: 10394732
    Abstract: An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. The interface device is provided with processing circuitry to generate the processed data from the incoming data wherein the processing carried out reduces the data in size. The processing circuitry is also responsive to at least one characteristic of the incoming data or the processed data to transmit a notification signal to a data processing component of the data processing system.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: August 27, 2019
    Assignee: ARM Limited
    Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, David Walter Flynn, Rohan Gaddh, Rohit Grover
  • Publication number: 20180032455
    Abstract: An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. The interface device is provided with processing circuitry to generate the processed data from the incoming data wherein the processing carried out reduces the data in size. The processing circuitry is also responsive to at least one characteristic of the incoming data or the processed data to transmit a notification signal to a data processing component of the data processing system.
    Type: Application
    Filed: July 26, 2016
    Publication date: February 1, 2018
    Inventors: Parameshwarappa Anand Kumar SAVANTH, James Edward MYERS, David Walter FLYNN, Rohan GADDH, Rohit GROVER
  • Patent number: 9704798
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Sridhar Govindaraju, Anindya Dasgupta, Rohit Grover
  • Patent number: 9472456
    Abstract: Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to remove titanium nitride, exposing the workpiece to a second solution to remove titanium, and exposing the workpiece to a third solution to remove residual titanium nitride, if any. The solutions are formulated such that they may selectively remove titanium and/or titanium nitride, while not etching or not substantially etching certain other materials such as dielectric materials, oxides, and metals other than titanium.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Erica J. Thompson, Nabil G. Mistkawi, Rohit Grover
  • Publication number: 20150179469
    Abstract: An embodiment includes forming a first film over first and second portions of a SOC, the first portion including a first density of structures and the second portion including a second density of structures with the first density being denser than the second density; forming a second film over the first film; polishing the second film to remove some of the second film and form (a) a first section of the second film between sections of the first film located over the first portion, and (b) a second section of the second film between sections of the second film located over the second portion; etching the first film over the first and second portions and etching the first and second sections of the second film; and polishing the first film to expose top surfaces of the structures of the first and second portions. Other embodiments are described herein.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Sridhar Govindaraju, Matthew J. Prince, Rohit Grover
  • Publication number: 20150179510
    Abstract: Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to remove titanium nitride, exposing the workpiece to a second solution to remove titanium, and exposing the workpiece to a third solution to remove residual titanium nitride, if any. The solutions are formulated such that they may selectively remove titanium and/or titanium nitride, while not etching or not substantially etching certain other materials such as dielectric materials, oxides, and metals other than titanium.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 25, 2015
    Inventors: ERICA J. THOMPSON, NABIL G. MISTKAWI, ROHIT GROVER
  • Publication number: 20150179567
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: Sridhar Govindaraju, Anindya Dasgupta, Rohit Grover
  • Publication number: 20080079166
    Abstract: Embodiments of semiconductor devices and methods of making such devices are presented herein.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Kevin J. Lee, Subhash Joshi, Angelo Kandas, Everett Branderhorst, Rohit Grover, Tzuen-Luh Huang
  • Publication number: 20030118948
    Abstract: A method of etching a semiconductor material by first selecting a substrate material. Next, patterning a mask layer onto the substrate. The substrate material over which the mask layer does not appear is then etched for a user-definable time. Any polymer that builds up on the sidewalls of the substrate material being etched is removed. If the substrate material has been etched and cleaned at least twice then stop. Otherwise, return to the substrate etch step for additional processing. The present invention performs a cleaning step to remove polymer that builds up on the sidewalls of the desired structure after etching only a portion of the desired depth of the resulting structure. Therefore, no polymer is allowed to build up and affect the verticality of the resulting structure.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 26, 2003
    Inventor: Rohit Grover