Abstract: An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

Abstract: A memory controller circuit receives memory access requests from a network of a computer system. Entries are reserved for these requests in a retry queue circuit. An arbitration circuit of the memory controller circuit issues those requests to a tag pipeline circuit that determines whether the received memory access requests hit in a memory cache. As a memory access request passes through the tag pipeline circuit, it may require another pass through this pipeline—for example, if resources such as certain storage circuits needed to complete the memory access request are unavailable (for example a snoop queue circuit). The reservation that has been made in the retry queue circuit thus keeps the request from having to be returned to the network for resubmission to the memory controller circuit if initial processing of the memory access request cannot be completed.

Abstract: Adjustable clock and power gating control is facilitated hereby. In aspects, a power management circuit is coupled to a memory controller circuit that is coupled to a memory resource circuit and to a plurality of heterogeneous client circuits configured to access the memory resource circuit via the memory controller circuit. The power management circuit is configured to receive operating parameters associated with the plurality of client circuits and to determine, based on the operating parameters, a threshold power state for the memory resource circuit. Additionally, the power management circuit is configured to initiate a clock gating operation, a power gating operation, or both for the memory resource circuit and to maintain at least the threshold power state for the memory resource circuit by limiting performance of the clock gating operation, the power gating operation, or both for the memory resource circuit. Other aspects and features are also claimed and described.

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

Abstract: Systems, methods, and devices are described that may mitigate pixel and touch crosstalk noise. A touch processing system may compensate touch scan data to reduce the noise based on a luminance value. An image processing system may determine the luminance value based on image data and a display brightness value of an electronic display. Using the compensated touch scan data, the touch processing system may determine a proximity of a capacitive object to at least one touch sense region of the electronic display.

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

Abstract: An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

Abstract: Embodiments relate to streaming convolution operations in a neural processor circuit that includes a neural engine circuit and a neural task manager. The neural task manager obtains multiple task descriptors and multiple subtask descriptors. Each task descriptor identifies a respective set of the convolution operations of a respective layer of a set of layers. Each subtask descriptor identifies a corresponding task descriptor and a subset of the convolution operations on a portion of a layer of the set of layers identified by the corresponding task descriptor. The neural processor circuit configures the neural engine circuit for execution of the subset of the convolution operations using the corresponding task descriptor. The neural engine circuit performs the subset of the convolution operations to generate output data that correspond to input data of another subset of the convolution operations identified by another subtask descriptor from the list of subtask descriptors.

Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

Abstract: In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

Abstract: Embodiments relate to streaming operations in a neural processor circuit that includes a neural engine circuit and a data processor circuit. The neural engine circuit performs first operations on a first input tensor of a first layer to generate a first output tensor, and second operations on a second input tensor of a second layer at a higher hierarchy than the first layer, the second input tensor corresponding to the first output tensor. The data processor circuit stores a portion of the first input tensor for access by the neural engine circuit to perform a subset of the first operations and generate a portion of the first output tensor. The data processor circuit stores the portion of the first output tensor for access by the neural engine circuit as a portion of the second input tensor to perform a subset of the second operations.

Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.