Patents by Inventor Rohit P. Thakar

Rohit P. Thakar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Combined conditional branch and indirect branch target predictor
    Patent number: 10776119
    Abstract: An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 15, 2020
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Edward J. McLellan, David A. Carlson, Rohit P. Thakar
  • Combined Conditional Branch and Indirect Branch Target Predictor
    Publication number: 20190384609
    Abstract: An example embodiment combines use of a branch predictor with cache-like storage of previously executed branch targets to improve processor performance while minimizing hardware cost. The branch predictor is configured to predict both conditional branch and indirect branch targets and includes a combined predictor table configured to store at least one tagged conditional branch prediction in combination with at least one tagged indirect branch target prediction. The at least one tagged indirect branch target prediction is configured to include a predicted partial target address of a complete target address, the complete target address associated with an indirect branch instruction of a processor. The predictor includes prediction logic configured to use the predicted partial target address to produce a predicted complete target address of the complete target address for use by the processor prior to execution of the indirect branch instruction.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Edward J. McLellan, David A. Carlson, Rohit P. Thakar