Patents by Inventor Rohit R. Verma

Rohit R. Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130083798
    Abstract: In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma, Robert P. Adler
  • Publication number: 20130086139
    Abstract: In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Sridhar Lakshmanamurthy, Robert P. Adler, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Rohit R. Verma
  • Publication number: 20130086288
    Abstract: In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Rohit R. Verma
  • Publication number: 20130086433
    Abstract: In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma
  • Publication number: 20080159532
    Abstract: In one embodiment, the present invention includes a method for receiving a first encrypted data stream in a cipher, receiving parsed condition information in a first state machine, where the parsed condition information corresponds to the first encrypted data stream, and decrypting the first encrypted data stream in the cipher responsive to control of the first state machine based on the parsed condition information. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventor: Rohit R. Verma
  • Patent number: 7308526
    Abstract: A memory controller module that includes a memory interface and at least two memory controllers, each memory controller to control a category of memory devices. A circuitry enables the at least two memory controllers to control access to memory devices based on information indicating the category or categories of the memory devices coupled to the memory interface.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Alpesh B. Oza, Rohit R. Verma
  • Patent number: 7203889
    Abstract: A memory controller includes a write data module to write user data, parity information, and error correction information in a memory. The memory controller includes a read data module to read the user data and parity information, determine whether there is error in the user data based on the parity information, read the error correction information if there is error as determined based on the parity information.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Alpesh B. Oza, Miguel A. Guerrero, Rohit R. Verma