Patents by Inventor Rohit Sathyanarayan

Rohit Sathyanarayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Storage system and method for improving read performance using multiple copies of a logical-to-physical address table
    Patent number: 10713157
    Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 14, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eyal Widder, Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, Indu Kumari, Abhinand Amarnath, Rohit Sathyanarayan
  • Storage System and Method for Improving Read Performance Using Multiple Copies of a Logical-to-Physical Address Table
    Publication number: 20190370167
    Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Eyal Widder, Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, lndu Kumari, Abhinand Amarnath, Rohit Sathyanarayan
  • Folding operations in memory systems with single address updates
    Patent number: 10275170
    Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, Satya Kesav Gundabathula, Ramkumar Ramamurthy, Rohit Sathyanarayan
  • FOLDING OPERATIONS IN MEMORY SYSTEMS WITH SINGLE ADDRESS UPDATES
    Publication number: 20180293014
    Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Balakumar Rajendran, Satya Kesav Gundabathula, Ramkumar Ramamurthy, Rohit Sathyanarayan