Patents by Inventor Rohit Shenoy

Rohit Shenoy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240354209
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
  • Patent number: 12106815
    Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: October 1, 2024
    Assignee: Intel Coproration
    Inventors: Ravi Motwani, Pranav Kalavade, Rohit Shenoy, Rifat Ferdous
  • Patent number: 12099420
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: September 24, 2024
    Assignee: Intel Corporation
    Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
  • Publication number: 20230352092
    Abstract: Systems, apparatuses and methods may provide for technology that issues a program pulse to a selected subblock of a NAND memory array, conducts a pulse recovery phase after the program pulse, and shuts down unselected subblocks in the NAND memory array during the pulse recovery phase.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: Tarek Ameen, Shantanu Rajwade, Hsiao Yu Chang, Rohit Shenoy, Pranav Chava, Xin Sun, Pratyush Chandrapati
  • Patent number: 11625191
    Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: April 11, 2023
    Assignee: Intel Corporation
    Inventors: Arash Hazeghi, Pranav Kalavade, Rohit Shenoy, Krishna Parat
  • Publication number: 20230044991
    Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 9, 2023
    Inventors: Shantanu Rajwade, Kartik Ganapathi, Rohit Shenoy, Kristopher Gaewsky, MarkAnthony Golez, Vivek Angoth, Pranav Kalavade, Sarvesh Gangadhar
  • Publication number: 20210240388
    Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: Arash Hazeghi, Pranav Kalavade, Rohit Shenoy, Krishna Parat
  • Publication number: 20210141703
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
  • Publication number: 20210082535
    Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. In one example, the first density and the second density are different from one another.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 18, 2021
    Inventors: Ravi Motwani, Pranav Kalavade, Rohit Shenoy, Rifat Ferdous
  • Publication number: 20190043567
    Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 28, 2018
    Publication date: February 7, 2019
    Inventors: Ali Khakifirooz, Shantanu Rajwade, Rohit Shenoy, Aliasgar Madraswala, Pranav Kalavade
  • Patent number: 8688491
    Abstract: Business management methods for on-demand trial based marketing and sales are introduced. Using on-demand trial technology, usage metrics can be automatically generated by tracking the usage of specific products and corresponding duration. Usage metrics and other data are automatically processed to qualify and channel leads to pertinent categories in sales and marketing. The present invention facilitates a more directed effort to investigate leads and makes the information of customers available for follow-up that has higher prospective sales potential. The present invention may also be used to dispatch pre-release reports automatically to a vendor.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: April 1, 2014
    Assignee: The Mathworks, Inc.
    Inventors: Rohit Shenoy, Pieter J. Mosterman, Bella G. Teverovsky, John Fluet, Craig Dowley
  • Patent number: 7996255
    Abstract: Business management methods for on-demand trial based marketing and sales are introduced. Using on-demand trial technology, usage metrics can be automatically generated by tracking the usage of specific products and corresponding duration. Usage metrics and other data are automatically processed to qualify and channel leads to pertinent categories in sales and marketing. The present invention facilitates a more directed effort to investigate leads and makes the information of customers available for follow-up that has higher prospective sales potential. The present invention may also be used to dispatch pre-release reports automatically to a vendor.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: August 9, 2011
    Assignee: The MathWorks, Inc.
    Inventors: Rohit Shenoy, Pieter J. Mosterman, Bella G. Teverovsky, John Fluet, Craig Dowley