Patents by Inventor Rohit Singh

Rohit Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12645272
    Abstract: A processor cluster includes a first processor core electrically coupled directly to a power rail and a second processor core coupled to the power rail through power switches. The first processor core consumes power due to leakage currents during idle states. The second processor core is electrically decoupled from the power rail during idle states by the power switches, but the power switches cause a performance degradation. A scheduler assigns tasks to the first processor core rather than the second processor core to maximize performance and minimize power consumption due to leakage currents. Some tasks may indicate that they can be executed on a lower-performance core type, which may be the core type of the second processor core, but those tasks may be assigned to the first processor core while the second processor core is turned off.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: June 2, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Rajesh Arimilli, Bharat Kumar Rangarajan, Raashid Moin Shaikh, Venkata Biswanath Devarasetty, Ramakrishna Gottimukkula, Rohit Singh
  • Publication number: 20260149514
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to receive one or more test results referencing changes of one or more performance parameters of a communication device over a period of time, determine one or more hardware testing operations that were performed on the communication device to obtain the test results, associate the test results and the hardware testing operations to communication device information associated with the communication device, retrieve one or more communication guidelines from a data retrieval interface associated with a manufacture year in the communication device information, correlate each of the test results to one or more of the hardware testing operations, generate a report comprising a visual depiction of a correlation of the test results and the hardware testing operations over the period of time, and transmit the report to the data retrieval interface.
    Type: Application
    Filed: November 27, 2024
    Publication date: May 28, 2026
    Inventors: Rohit Singh, Joshua Garcia De La Torre, Levi Simeon Eichelberg
  • Publication number: 20260149752
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to access one or more release versions of one or more services matching the communication device information, copy a first release version onto a centralized data repository, transform a predefined format of the first release version to a localized format that associates the first release version to the centralized data repository, parse the first release version to determine information elements, categorize each information element, generate release triggers for each information element in accordance with corresponding priority tiers, attach the release triggers to the first release version comprising the localized format in the centralized data repository, generate a report referencing that the first release version is available for installing at the centralized data repository, and broadcast the report to the at least one communication device matching the communication device information.
    Type: Application
    Filed: November 27, 2024
    Publication date: May 28, 2026
    Inventors: Rohit Singh, Joshua Garcia De La Torre, Levi Simeon Eichelberg
  • Publication number: 20260086614
    Abstract: Certain aspects of the present disclosure are directed towards techniques and apparatus for power control. An example apparatus generally includes a memory configured to consume power from a first voltage rail and a controller configured to: detect whether current consumption from the first voltage rail is greater than or equal to a current threshold; determine whether a voltage of a second voltage rail is greater than a voltage threshold in response to the current consumption being greater than or equal to the current threshold; and cause the memory to consume current from the second voltage rail instead of the first voltage rail based on the voltage being greater than the voltage threshold.
    Type: Application
    Filed: September 20, 2024
    Publication date: March 26, 2026
    Inventors: Sreeharipriya GARIKIPATI, Pragya PANDE, Rohit SINGH, Ankur MEHROTRA, Srikar KARNAM VENKAT NAGA, Prasad Rao KOLETI
  • Publication number: 20260082352
    Abstract: A disclosed method may include receiving, by a server of a mobile operator, a location information message from a user equipment device that the user equipment device sent in response to the user equipment device powering on such that the location information message indicates a location of the user equipment device and matching, by the mobile operator, the location of the user equipment device that was indicated by the location information message sent by the user equipment device to a specific geofenced area from among a plurality of geofenced areas defined by the mobile operator.
    Type: Application
    Filed: September 19, 2024
    Publication date: March 19, 2026
    Inventors: Nikhil Rangaraajan Vijayakumar, Rohit Singh
  • Publication number: 20260059519
    Abstract: Systems and methods for network-based intelligent multicasting in cellular networks are disclosed. User Grouping Criteria (UGC) are generated for User Equipment (UEs) within a cell. The base station determines a group of UEs capable of device-to-device (D2D) communication that satisfy the UGC. Multicasting transmissions for the group are scheduled using D2D communication, facilitating direct communication without routing data through the base station. The UGC considers factors including UE capabilities, measurement reports, Channel Quality Indicators (CQI), locations, and directionality. Error management and retransmission protocols ensure reliable D2D communication. The system facilitates optimization of network resource utilization, reduces base station load, and improves spectral efficiency by utilizing D2D capabilities for multicasting in scenarios where multiple UEs are in close proximity.
    Type: Application
    Filed: September 9, 2024
    Publication date: February 26, 2026
    Inventor: Rohit Singh
  • Publication number: 20260050961
    Abstract: In various examples, systems and techniques are provided that are directed to processing, using a language model, a user query associated with an artificial intelligence (AI) task. The system and techniques are used to obtain a recommendation to use, in performance of the AI task, one or more AI services—such as inference microservices—provided by, for example, a cloud AI server.
    Type: Application
    Filed: August 14, 2024
    Publication date: February 19, 2026
    Inventors: Vishal Dhar, Ankita Bajaj, Umer Ahsan, Abhishek Anurag, Rohit Singh
  • Patent number: 12549182
    Abstract: Aspects of the disclosure are directed to dc power consumption optimization in an extended reality (XR) device with thermal constraints. In accordance with one aspect, the disclosure includes performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.
    Type: Grant
    Filed: June 10, 2024
    Date of Patent: February 10, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Sreeharipriya Garikipati, Pragya Pande, Ankur Mehrotra, Rohit Singh
  • Patent number: 12530064
    Abstract: Aspects relate to mechanisms for providing a power aware thermal mitigation framework for a system-on-chip (SoC) of a device (e.g., a mobile device). A thermal controller of the SoC is configured to calculate a respective power of each of a plurality of electronic control units (ECUs) on the SoC at run time. The ECUs may include, for example, central processing units (CPUs), graphic processing units (GPUs), neural signal processors (NSPs), etc. In response to a skin temperature of the device exceeding a threshold (e.g., a thermal limit of the device), the thermal controller may then be configured to apply at least one thermal mitigation action to at least one ECU of the plurality of ECUs based on the respective power of each of the ECUs.
    Type: Grant
    Filed: January 31, 2024
    Date of Patent: January 20, 2026
    Assignee: Qualcomm Incorporated
    Inventors: Lakshmi Kanth Boddu, Rohit Singh, Srikar Karnam Venkat Naga
  • Publication number: 20260004725
    Abstract: Dynamically controlling the display brightness of a smartphone to reduce power consumption using facial detection via an always-on camera. The smartphone is equipped with a dedicated low-power always-on (AON) camera system that performs facial detection to determine whether the user is actively looking at the screen. When the user is not looking at the screen, the display brightness is automatically lowered to a preset level or by a percentage to reduce display power consumption. When the user's face is subsequently detected, the brightness is increased based on ambient light sensor readings. The AON camera system enables power optimization while also supporting instant face unlock, hands-free convenience features, and enhanced security. By dynamically adjusting the display brightness based on user engagement, battery life is significantly extended without compromising the user experience.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Inventors: Vandit Chauhan, Sreeharipriya Garikipati, Pragya Pande, Rohit Singh, Ankit Kumar, Mrinal Gupta
  • Publication number: 20260003636
    Abstract: This disclosure provides methods, components, devices and systems for process-aware boot-up. An example method, performed at a system-on-a-chip (SoC), generally includes obtaining parameters associated with estimated boot-up power consumption for different parts of the SoC, and setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure, based on the corresponding parameters.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Inventors: Pragya PANDE, Rohit SINGH, Vandit CHAUHAN, Amit GARG, Udit BANSAL, Yashaswini N
  • Publication number: 20250379578
    Abstract: Aspects of the disclosure are directed to dc power consumption optimization in an extended reality (XR) device with thermal constraints. In accordance with one aspect, the disclosure includes performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.
    Type: Application
    Filed: June 10, 2024
    Publication date: December 11, 2025
    Inventors: Sreeharipriya GARIKIPATI, Pragya PANDE, Ankur MEHROTRA, Rohit SINGH
  • Publication number: 20250377705
    Abstract: Various embodiments include a method performed by a processor system of a computing device for managing power modes of the processor system. Embodiments may include identifying a minimum residency time of a low-power mode of the processor system based on actual current leakage at runtime of the processor system, identifying a cost of the low-power mode based in part on the minimum residency time of the low-power mode, determining based on the cost of the low-power mode whether transitioning to the low-power mode will result in cost savings as compared to a cost of operating in at least one other power mode of the processor system, and configuring the processor system for the low-power mode in response to determining that transitioning to the low-power mode will result in cost savings. Cost savings may be energy savings, performance savings, latency savings, or other forms of measurable costs.
    Type: Application
    Filed: June 5, 2024
    Publication date: December 11, 2025
    Inventors: Rohit SINGH, Venkata Biswanath DEVARASETTY, Srinivas Rao LENGAMANENI, Ashok Kumar JANDRAPETA, Chethan MURARISHETTY, Maheshwar Thakur SINGH, Linga Achuta Ram Kumar NIMMALA, Nilesh DHAVLIKAR
  • Patent number: 12455854
    Abstract: The present invention discloses a file storage system including an object storage for storing data blocks for a client, a merge index database to store metadata corresponding to the stored data blocks using a merge index, a cloudcache located on a premise of the client, and a cloudcache implementation module communicatively coupled to the object storage, the cloudcache and the merge index database. The cloudcache implementation module facilitates data backup and restore operations for the client in accordance with a data retention policy, where one or more data blocks are stored on the cloudcache and a sync operation is performed between the cloudcache and the object storage. A backup of the data blocks is performed to the cloudcache in a backup operation, data blocks are compacted, and a restore operation for data blocks stored on the cloudcache are performed in accordance with the data retention policy.
    Type: Grant
    Filed: January 16, 2024
    Date of Patent: October 28, 2025
    Assignee: Druva Inc.
    Inventors: Somesh Jain, Rohit Singh, Shubham Agarwal, Saurabh Bhavsar
  • Publication number: 20250312357
    Abstract: The present invention relates to the process of enrichment of Phytocannabinoids namely CBD and ?9-THC from the dried aerial part (leaves and inflorescence) of Cannabis sativa. The present invention also relates to the preparation of formulation having enriched CBD and THC by combining with appropriate acceptable excipients such as nutriose, dextrin and maltodextrin. The present invention also discloses the use of the phytocannabanoids enriched blend for the management of pain including cancer pain & general pain.
    Type: Application
    Filed: May 16, 2023
    Publication date: October 9, 2025
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Pankaj Singh CHAM, Manmeet SINGH, Aman VERMA, Radhika ANAND, Rohit SINGH, Kuhu SHARMA, Pankul KOTWAL, Abhishek GOUR, Pankaj KUMAR, Durga Prasad MINDALA, Sumit ROY, Chandra Pal SINGH, Siya Ram MEENA, Ajay KUMAR, Mahendra Kumar VERMA, Vishav Prakash RAHUL, Utpal NANDI, Sumeet GAIROLA, Anil Kumar KATARE, Deepika SINGH, Pyare Lal SANGWAN, Dhiraj VYAS, Sanghapal Damodhar SAWANT, Gurdarshan SINGH, Vishwakarma Ram ASREY, Dumbala Srinivasa REDDY, Parvinder Pal SINGH
  • Publication number: 20250269349
    Abstract: A spacer array including a plurality of spacers. Each spacer defines a longitudinal axis and includes a main body, a leading pin, and a trailing pin. The main body has a main body cross-sectional dimension. The leading pin extends from the main body and is upstream of the main body. The leading pin has a leading pin cross-sectional dimension. The trailing pin extends from the main body and is downstream of the main body. The trailing pin has a trailing pin cross-sectional dimension. The main body cross-sectional dimension is greater than the leading pin cross-sectional dimension and the trailing pin cross-sectional dimension.
    Type: Application
    Filed: February 20, 2025
    Publication date: August 28, 2025
    Inventors: Shane Lawson, Christopher P. Conklin, Benjamin C. Druecke, Alexander E. Mottet, Kristof Decoster, Yehya A. Elsayed, Abhishek Maharia, Rohit Singh, Elena T. Ewaldz, Laurent Coustenoble
  • Publication number: 20250269307
    Abstract: A volumetric media having an upstream end and a downstream end. The volumetric media includes one or more spacers and a packing material around the spacers. The packing material includes a foam. The packing material may include fine fibers disposed on at least a portion of the foam.
    Type: Application
    Filed: February 20, 2025
    Publication date: August 28, 2025
    Inventors: Shane Lawson, Christopher P. Conklin, Benjamin C. Druecke, Alexander E. Mottet, Kristof Decoster, Yehya A. Elsayed, Abhishek Maharia, Rohit Singh, Elena T. Ewaldz, Laurent Coustenoble
  • Publication number: 20250244806
    Abstract: Aspects relate to mechanisms for providing a power aware thermal mitigation framework for a system-on-chip (SoC) of a device (e.g., a mobile device). A thermal controller of the SoC is configured to calculate a respective power of each of a plurality of electronic control units (ECUs) on the SoC at run time. The ECUs may include, for example, central processing units (CPUs), graphic processing units (GPUs), neural signal processors (NSPs), etc. In response to a skin temperature of the device exceeding a threshold (e.g., a thermal limit of the device), the thermal controller may then be configured to apply at least one thermal mitigation action to at least one ECU of the plurality of ECUs based on the respective power of each of the ECUs.
    Type: Application
    Filed: January 31, 2024
    Publication date: July 31, 2025
    Inventors: Lakshmi Kanth BODDU, Rohit SINGH, Srikar KARNAM VENKAT NAGA
  • Patent number: 12332711
    Abstract: A system for performing peak current mitigation in an application programming subsystem (APSS) dynamically performs mitigation based at least in part on power rail voltage and leakage current obtained at boot time. The voltage and leakage current obtained at boot time are used to estimate peak current. A map that is generated prior to boot time maps estimated peak current to throttling level and dictates different levels of throttling to be performed for different ranges of estimated peak current. At boot time, the map is used to map the estimated peak current to a level of throttling to be applied. If conditions at run time indicate that peak current is occurring or is likely to occur soon, the mapped level of throttling is applied to mitigate the peak current.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: June 17, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Srikar Karnam Venkat Naga, Vandit Chauhan, Venkata Naga Satya Srinivas Nudurupati, Karimulla Syed, Rohit Singh, Virat Deepak, Satyaki Mukherjee, Ashok Kumar Immadi, Ronald Alton
  • Publication number: 20250172980
    Abstract: A processor cluster includes a first processor core electrically coupled directly to a power rail and a second processor core coupled to the power rail through power switches. The first processor core consumes power due to leakage currents during idle states. The second processor core is electrically decoupled from the power rail during idle states by the power switches, but the power switches cause a performance degradation. A scheduler assigns tasks to the first processor core rather than the second processor core to maximize performance and minimize power consumption due to leakage currents. Some tasks may indicate that they can be executed on a lower-performance core type, which may be the core type of the second processor core, but those tasks may be assigned to the first processor core while the second processor core is turned off.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Inventors: Rajesh Arimilli, Bharat Kumar Rangarajan, Raashid Moin Shaikh, Venkata Biswanath Devarasetty, Ramakrishna Gottimukkula, Rohit Singh