Abstract: A method of operating a motor vehicle includes a vehicle controller receiving, from a first feedback sensor of an HV component, a first feedback signal indicative of an electrical characteristic of the HV component, and then detecting an HV system fault if the first feedback signal is less than a predefined electrical threshold. Upon detecting the system fault, the controller commands the HV component to operate at a commanded set-point; after sending the command, the controller receives, from a second feedback sensor of the HV component, a second feedback signal indicative of an operating characteristic of the HV component. An HV pathway failure is detected if the second feedback signal is not equal to or within a predefined operating range of the commanded set-point. Upon detecting the pathway failure in an HV electrical pathway of the HV component, the vehicle controller transmits a command signal to take a remedial action.

Abstract: The embodiments herein provide an onboard track switching mechanism for a railroad vehicle to switch from one track to another. Currently available onboard railroad vehicle switching mechanisms employ complicated coordination between one or more switching wheels and complex control systems. Accordingly, system and method for enabling a railroad vehicle to switch tracks is disclosed. The system comprises a a running track that supports an automotive a switching track comprising a set of static components and a switching mechanism installed on the automotive. the switching mechanism configured for controlling the movement of one or more switching wheels such that when activated, the switching mechanism is configured to facilitate engagement of the one or more switching wheels with the switching track for carrying out a track changing operation for the automotive.

Abstract: An apparatus for dynamic voltage and frequency scaling. The apparatus includes a plurality of voltage rails supplying a plurality of voltages for a system on a chip (SoC). The apparatus includes a plurality of engines integrated within the SoC. The plurality of engines is coupled to the plurality of voltage rails. The apparatus includes an on-chip dynamic voltage and frequency scaling (DVFS) module coupled to the plurality of engine. The DVFS module is configured to selectively couple each of the plurality of engines to one of the plurality of voltage rails depending on a corresponding performance request of a plurality of performance requests from the plurality of engines.

Abstract: An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.

Abstract: A system for buffering a video signal is provided. The system includes a graphics processing unit (GPU), the GPU generating the video signal, and a buffering circuit coupled to the GPU, the buffering circuit receiving and temporarily storing the video signal when the GPU enters a power saving mode. The system also includes a display device coupled to the bridge circuit and receiving the video signal from the buffering circuit. The buffering circuit includes an internal memory device configured to temporarily store a first portion of the video signal, and an external memory device configured to temporarily store a second portion of the video signal. A circuit and method for buffering a video signal are also provided.

Abstract: Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.

Abstract: Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.

Abstract: An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.