Abstract: According to embodiments of the invention, a system, method and computer program product producing spike-dependent plasticity in an artificial synapse.

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.

Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.

Abstract: A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2N semiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2N semiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2N semiconductor regions are selected.