Patents by Inventor Rohit Taneja

Rohit Taneja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180088918
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. The processor defines a special store instruction that is different from a regular store instruction. The special store instruction is used in regions of the computer program where memory aliasing may occur. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing may occur.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Publication number: 20180081647
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 22, 2018
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Publication number: 20170351497
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Publication number: 20170351495
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The result is code that is more optimized and therefore runs faster.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Publication number: 20170351496
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. The processor defines a special store instruction that is different from a regular store instruction. The special store instruction is used in regions of the computer program where memory aliasing may occur. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing may occur.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Inventors: Srinivasan Ramani, Rohit Taneja
  • Publication number: 20170351498
    Abstract: Processor hardware detects when memory aliasing occurs, and assures proper operation of the code even in the presence of memory aliasing. Because the hardware can detect and correct for memory aliasing, this allows a compiler to make optimizations such as register promotion even in regions of the code where memory aliasing can occur. The compiled code is then executed on the processor hardware, which detects memory aliasing at run-time and assures proper operation of the code even when memory aliasing occurs.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Inventors: Srinivasan Ramani, Rohit Taneja