Patents by Inventor Rohit Tomar
Rohit Tomar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10303736Abstract: An FFT device for performing a Fast Fourier Transform (FFT) is described. The FFT device comprises: a control unit arranged to control a sequence of transformation rounds; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. The coefficient unit comprises or is integrated in a Random Access Memory (RAM) unit, the RAM unit comprising a set of memory blocks. The set of memory blocks comprises: a subset of window memory blocks or a subset of window-FFT memory blocks. The set of memory blocks further comprises a subset of FFT memory blocks providing a set of twiddle coefficients or a reduced set of twiddle coefficients.Type: GrantFiled: December 16, 2013Date of Patent: May 28, 2019Assignee: NXP USA, Inc.Inventors: Maik Brett, Navdeep Singh Gill, Rohit Tomar
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Patent number: 10282387Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data. The transformation unit is arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.Type: GrantFiled: November 6, 2013Date of Patent: May 7, 2019Assignee: NXP USA, Inc.Inventors: Maik Brett, Navdeep Singh Gill, Rohit Tomar
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Patent number: 10209345Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.Type: GrantFiled: October 21, 2013Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Maik Brett, Deboleena Sakalley, Rohit Tomar
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Patent number: 9740663Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.Type: GrantFiled: May 21, 2014Date of Patent: August 22, 2017Assignee: NXP USA, Inc.Inventors: Rohit Tomar, Maik Brett, Tejbal Prasad, Gurinder Singh
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Publication number: 20170132175Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described.Type: ApplicationFiled: December 16, 2013Publication date: May 11, 2017Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Maik BRETT, Navdeep Singh GILL, Rohit TOMAR
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Publication number: 20160314096Abstract: And FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data.Type: ApplicationFiled: November 6, 2013Publication date: October 27, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Maik BRETT, Navdeep Singh GILL, Rohit TOMAR
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Publication number: 20160266238Abstract: A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.Type: ApplicationFiled: October 21, 2013Publication date: September 15, 2016Inventors: Maik BRETT, Deboleena SAKALLEY, Rohit TOMAR
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Publication number: 20160124904Abstract: A data processing device and a method for performing a round of an N point Fast Fourier Transform are described. The round comprises computing N output operands on the basis of N input operands by applying a set of N/P radix-P butterflies to the N input operands, wherein P is greater or equal two and the input operands are representable as N/(M*P)?2 input operand matrices, wherein M is greater or equal one, each input operand matrix is a square matrix with M*P lines and M*P columns, and each column of each input operand matrix contains the input operands for M of said butterflies.Type: ApplicationFiled: June 17, 2013Publication date: May 5, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Rohit TOMAR, Aman ARORA, Maik BRETT, Deboleena SAKALLEY
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Patent number: 9292380Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.Type: GrantFiled: April 6, 2014Date of Patent: March 22, 2016Assignee: FREESCALE SEMICONDUCTOR,INC.Inventors: Nitin Singh, Gaurav Jain, Amit Jindal, Rohit Tomar
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Publication number: 20150339264Abstract: A data processing device and a method for performing second or next stage of an N point Fast Fourier Transform is suggested. The processing device comprises an input operand memory unit and an input buffer comprising a plurality of addressable memory cells arranged in lines and columns. Furthermore, the device comprises a number of radix-P operation units for producing output operands that are buffered in an output buffer. Input operands are read from the input operand memory unit and buffering into the input buffer. The input operands are stored and fetched from the input buffer according to a reordering scheme that allows efficient parallel processing of the operands by the butterflies and the buffering of subsequent input operands.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ROHIT TOMAR, MAIK BRETT, TEJBAL PRASAD, GURINDER SINGH
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Publication number: 20150286525Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.Type: ApplicationFiled: April 6, 2014Publication date: October 8, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Nitin Singh, Gaurav Jain, Amit Jindal, Rohit Tomar
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Patent number: 9031736Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.Type: GrantFiled: January 8, 2014Date of Patent: May 12, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Rohit Tomar, Prashant Bhargava, Neha Jain, Matthew B. Ruff
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Publication number: 20140121886Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Inventors: Rohit Tomar, Prashant Bhargava, Neha Jain, Matthew B. Ruff
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Patent number: 8645020Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.Type: GrantFiled: June 21, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Rohit Tomar, Prashant Bhargava, Neha Jain, Matthew B. Ruff
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Publication number: 20130345924Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.Type: ApplicationFiled: June 21, 2012Publication date: December 26, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Rohit Tomar, Prashant Bhargava, Neha Jain, Matthew B. Ruff
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Patent number: 8447004Abstract: A method and system for estimating and compensating for variation between a receiver clock and a transmitter clock, where a receiver utilizes a high frequency clock signal to generate a receiver clock and then adjusts the receiver clock to compensate for variations between the receiver and transmitter clocks. The adjusted receiver clock is used to sample nibble pulses in a received data frame. Counter based compensation of the receiver clock eliminates the need for the receiver to perform floating point calculations, improves the accuracy of nibble pulse sampling and also reduces area and power consumption of the device.Type: GrantFiled: February 4, 2011Date of Patent: May 21, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Rohit Tomar, Prashant Bhargava
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Publication number: 20120195400Abstract: A method and system for estimating and compensating for variation between a receiver clock and a transmitter clock, where a receiver utilizes a high frequency clock signal to generate a receiver clock and then adjusts the receiver clock to compensate for variations between the receiver and transmitter clocks. The adjusted receiver clock is used to sample nibble pulses in a received data frame. Counter based compensation of the receiver clock eliminates the need for the receiver to perform floating point calculations, improves the accuracy of nibble pulse sampling and also reduces area and power consumption of the device.Type: ApplicationFiled: February 4, 2011Publication date: August 2, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Rohit Tomar, Prashant Bhargave