Abstract: An oscillator/amplifier has a gain controlled amplifier that maintains a desired oscillation waveform amplitude for all possible oscillation frequencies of operation. A peak detector produces a direct current (DC) voltage proportional to the oscillation waveform, and a voltage reference generator provides a reference voltage that is compared against the DC voltage from the peak detector. When the DC voltage is less than the reference voltage the gain of the amplifier is increased, and when the DC voltage is equal to or greater than the reference voltage the gain of the amplifier is decreased. A programmable voltage reference generator may also be used to provide for selection of different oscillation waveform amplitudes. A digital control loop controls the oscillation waveform amplitude over the entire possible frequency range of operation. Various frequency determining elements, e.g., crystal, piezoelectric resonator, inductor-capacitor tuned circuit, resistor-capacitor network, etc.

Abstract: An oscillator/amplifier has a gain controlled amplifier that maintains a desired oscillation waveform amplitude for all possible oscillation frequencies of operation. A peak detector produces a direct current (DC) voltage proportional to the oscillation waveform, and a voltage reference generator provides a reference voltage that is compared against the DC voltage from the peak detector. When the DC voltage is less than the reference voltage the gain of the amplifier is increased, and when the DC voltage is equal to or greater than the reference voltage the gain of the amplifier is decreased. A programmable voltage reference generator may also be used to provide for selection of different oscillation waveform amplitudes. A digital control loop controls the oscillation waveform amplitude over the entire possible frequency range of operation. Various frequency determining elements, e.g., crystal, piezoelectric resonator, inductor-capacitor tuned circuit, resistor-capacitor network, etc.

Abstract: A receiver for high-speed indirect synchronous digital data transmission includes an elastic buffer receiving an incoming data stream containing embedded timing information preceding a data sequence, generating a recovered clock from the timing information, initially synchronizing the frequency of a local clock to the recovered clock, and accommodating subsequent drift between the recovered and local clocks across the duration of the data sequence while tolerating clock jitter. Received data is clocked into a FIFO buffer within the elastic buffer based on the recovered clock and read out based upon the local clock, with the buffer expanding or contracting by adjustment of an index to accommodate skew of greater than one clock period. Expansion or contraction of the FIFO buffer is disabled during periods when clock jitter is likely, such as periods immediately following an index change.