Patents by Inventor Roi M. Shor

Roi M. Shor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10582414
    Abstract: A method including receiving, by a radio equipment control (REC) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (RE) device at a first data transmission rate. The method further including transforming, by the REC device, the time domain compressed data to frequency domain decompressed full rate data for a second transmission data rate utilizing a Fast Fourier processing engine of the REC device.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: March 3, 2020
    Assignee: NXP USA, Inc.
    Inventors: Roi M. Shor, Avraham Horn, Yael Rozin
  • Publication number: 20170289842
    Abstract: A method including receiving, by a radio equipment control (REC) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (RE) device at a first data transmission rate. The method further including transforming, by the REC device, the time domain compressed data to frequency domain decompressed full rate data for a second transmission data rate utilizing a Fast Fourier processing engine of the REC device.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Roi M. Shor, Avraham Horn, Yael Rozin
  • Patent number: 9749161
    Abstract: A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ?, ?, ?) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 29, 2017
    Assignee: NXP USA, Inc.
    Inventors: Avraham D. Gal, Roi M. Shor, Igor Levakov
  • Publication number: 20170244582
    Abstract: A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter (224) which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, ?, ?, ?) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 24, 2017
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Avraham D. Gal, Roi M. Shor, Igor Levakov
  • Patent number: 9667455
    Abstract: An equalizer circuit of a particular equalization stage of a equalizer circuit is omitted, and input signals that would have otherwise been received at the omitted equalization circuit bypass the equalization stage and are instead processed at an equalizer circuit included at the next stage. Thus, a subset of the received frequency-domain signals can be processed by equalizer circuits at a first stage, while the remaining received frequency-domain signals bypass the first stage and are processed at an equalizer circuit included at a second stage.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: May 30, 2017
    Assignee: NXP USA, Inc.
    Inventors: Igor Levakov, Haim Bareket, Roi M. Shor
  • Patent number: 9252821
    Abstract: A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (371-372, 373-374) for combining the LUT output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yQ from said predistorter cell, where the output signal samples yQ from the predistorter cells are combined at an output adder circuit (375) to generate one or more Volterra terms of a combined signal (yOUT[n]).
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 2, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Roi M. Shor, Avraham D. Gal, Peter Z. Rashev
  • Publication number: 20150381216
    Abstract: A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (371-372, 373-374) for combining the LUT output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yQ from said predistorter cell, where the output signal samples yQ from the predistorter cells are combined at an output adder circuit (375) to generate one or more Volterra terms of a combined signal (yOUT[n]).
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Roi M. Shor, Avraham D. Gal, Peter Z. Rashev