Abstract: A method performed by a radio equipment control (REC) device, including storing values of link configuration registers of a radio equipment control (REC) device at shadow registers of the REC device in response to determining that a synchronization of a current communication link between the REC device and a radio equipment (RE) device has been lost. The method further including re-establishing the current communication link based on the values of the link configuration registers stored at the shadow registers of the REC device.

Abstract: A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first REC synchronization signal to a RE and when a REC receives a first RE synchronization signal back, wherein frames transmitted by the REC are synchronized based upon the first REC synchronization signal, and frames transmitted by the RE are synchronized based upon the first RE synchronization signal. Calculating a first delay change value between the first round trip delay value and a previous round trip delay value, in response to determining that the first delay change value violates a delay tolerance value, transmitting an offset indicator that indicates an amount of offset the RE is to shift the first RE synchronization signal at a future time, and transmitting frames from the REC after shifting the first REC synchronization signal.

Abstract: A method performed by a radio base station, the method including determining a link configuration of a first communication link, the first communication link being a current communication link between a first radio equipment control (REC) device and a radio equipment (RE) device. The method further including in response to determining that a second communication link between a second REC device and the RE device is to replace the current communication link, instead of the first communication link, establishing, by the second REC device, the second communication link based on the determined link configuration of the first communication link.

Abstract: A method performed by a radio base station, the method including receiving streaming data information, the data information includes a first portion from a first set of antenna carriers and a second portion from a second set of antenna carriers, wherein the first portion is to be processed prior to the second portion. The method further including streaming the first portion of the data information from a radio equipment control device in a first data frame over an interface link that is configured to operate based on a first mapping configuration that indicates a set of locations of the first data frame at which the first portion of information is to be streamed, and streaming the second portion of the data information from the REC device in a second data frame over the interface link that is configured to operate based on a second mapping configuration.

Abstract: The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Sizetrans, representative of an accumulated size of DMA transactions performed by a DMA controller in response to symbols transferred on a CPRI link from or to the CPRI lane controller. The symbol counter is provided for maintaining a current aggregated expected symbols' size, Sizeexp, representative of an accumulated size of a sequence of transferred symbols and a currently transferred symbol. The comparator is configured to issue a symbol awareness signal, SAS, in case the current aggregated transactions' size, Sizetrans, exceeds the current aggregated expected symbols' size, Sizeexp.

Abstract: A method performed by a radio base station, the method including determining that one of a Direct Memory Access (DMA) buffers of a communication link for a service provider has gone beyond a DMA buffer limit (empty or full), the communication link between a radio equipment control (REC) device and a radio equipment (RE) device that is operating based on a first bandwidth configuration of the communication link. The method further including in response to determining that the communication link is to change operation (due to reaching the DMA buffer limit) based on a second bandwidth configuration of the communication link, instead of the first bandwidth configuration, continuing operation of the communication link based on the second bandwidth configuration. The method further including that after going back under the DMA buffer limit, the communication link continuing operation based on the original first bandwidth configuration.

Abstract: The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Sizetrans, representative of an accumulated size of DMA transactions performed by a DMA controller in response to symbols transferred on a CPRI link from or to the CPRI lane controller. The symbol counter is provided for maintaining a current aggregated expected symbols' size, Sizeexp, representative of an accumulated size of a sequence of transferred symbols and a currently transferred symbol. The comparator is configured to issue a symbol awareness signal, SAS, in case the current aggregated transactions' size, Sizetrans, exceeds the current aggregated expected symbols' size, Sizeexp.

Abstract: An equalizer includes an equalizer circuit including a signal input to receive a first frequency-domain signal, another signal input to receive a second frequency-domain signal, and an equalized signal output to provide a first equalized signal based upon the first and second frequency-domain signals. Another equalizer circuit includes a signal input to receive a third frequency-domain signal, another signal input to receive a fourth frequency-domain signal, and an equalized signal output to provide a second equalized signal based upon the third and fourth frequency-domain signals. A third equalizer circuit includes a signal input coupled to the equalized signal output of the first equalizer circuit to receive the first equalized signal, another signal input coupled to the equalized signal output of the second equalizer circuit to receive the second equalized signal, and an equalized signal output to provide a third equalized signal based upon the first and second equalized signals.

Abstract: A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first REC synchronization signal to a RE and when a REC receives a first RE synchronization signal back, wherein frames transmitted by the REC are synchronized based upon the first REC synchronization signal, and frames transmitted by the RE are synchronized based upon the first RE synchronization signal. Calculating a first delay change value between the first round trip delay value and a previous round trip delay value, in response to determining that the first delay change value violates a delay tolerance value, transmitting an offset indicator that indicates an amount of offset the RE is to shift the first RE synchronization signal at a future time, and transmitting frames from the REC after shifting the first REC synchronization signal.

Abstract: A method performed by a radio base station, the method including receiving streaming data information, the data information includes a first portion from a first set of antenna carriers and a second portion from a second set of antenna carriers, wherein the first portion is to be processed prior to the second portion. The method further including streaming the first portion of the data information from a radio equipment control device in a first data frame over an interface link that is configured to operate based on a first mapping configuration that indicates a set of locations of the first data frame at which the first portion of information is to be streamed, and streaming the second portion of the data information from the REC device in a second data frame over the interface link that is configured to operate based on a second mapping configuration.

Abstract: A method performed by a radio base station, the method including determining that one of a Direct Memory Access (DMA) buffers of a communication link for a service provider has gone beyond a DMA buffer limit (empty or full), the communication link between a radio equipment control (REC) device and a radio equipment (RE) device that is operating based on a first bandwidth configuration of the communication link. The method further including in response to determining that the communication link is to change operation (due to reaching the DMA buffer limit) based on a second bandwidth configuration of the communication link, instead of the first bandwidth configuration, continuing operation of the communication link based on the second bandwidth configuration. The method further including that after going back under the DMA buffer limit, the communication link continuing operation based on the original first bandwidth configuration.

Abstract: A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output. The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the plurality of LUTs; and generate an output signal, y[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element.

Abstract: An equalizer comprises an equalizer circuit including a signal input to receive a first frequency-domain signal, another signal input to receive a second frequency-domain signal, and an equalized signal output to provide a first equalized signal based upon the first and second frequency-domain signals. Another equalizer circuit includes a signal input to receive a third frequency-domain signal, another signal input to receive a fourth frequency-domain signal, and an equalized signal output to provide a second equalized signal based upon the third and fourth frequency-domain signals. A third equalizer circuit includes a signal input coupled to the equalized signal output of the first equalizer circuit to receive the first equalized signal, another signal input coupled to the equalized signal output of the second equalizer circuit to receive the second equalized signal, and an equalized signal output to provide a third equalized signal based upon the first and second equalized signals.

Abstract: A method performed by a radio base station, the method including determining a link configuration of a first communication link, the first communication link being a current communication link between a first radio equipment control (REC) device and a radio equipment (RE) device. The method further including in response to determining that a second communication link between a second REC device and the RE device is to replace the current communication link, instead of the first communication link, establishing, by the second REC device, the second communication link based on the determined link configuration of the first communication link.

Abstract: A method performed by a radio equipment control (REC) device, including storing values of link configuration registers of a radio equipment control (REC) device at shadow registers of the REC device in response to determining that a synchronization of a current communication link between the REC device and a radio equipment (RE) device has been lost. The method further including re-establishing the current communication link based on the values of the link configuration registers stored at the shadow registers of the REC device.

Abstract: A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.

Abstract: A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse Fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a Fourier transform unit for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.

Abstract: A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse Fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a Fourier transform unit, for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.

Abstract: A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the, plurality of LUTs; and generate an output signal, y[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element.

Abstract: A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.