Patents by Inventor Roi N. Peers, Jr.

Roi N. Peers, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5581045
    Abstract: A four-operator sound synthesis integrated circuit comprises a first through a fourth sound synthesis operator, a first programmable multiplier connecting the output of the first operator to the input of the second operator, a second programmable multiplier connecting the output of the second operator to the input of the third operator, a third programmable multiplier connecting the output of the third operator to the input of the fourth operator, a fourth programmable multiplier connecting the output of the first operator a first input of a four-input adder, a fifth programmable multiplier connecting the output of the second operator a second input of the four-input adder, a sixth programmable multiplier connecting the output of the third operator a third input of the four-input adder, and a seventh programmable multiplier connecting the output of the fourth operator a fourth input of the four-input adder. The product of the combination is taken from the output of the four-input adder.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: December 3, 1996
    Assignee: ESS Technology, Inc.
    Inventor: Roi N. Peers, Jr.
  • Patent number: 5578779
    Abstract: A tone generator clears all registers in a twenty-nine stage device so that the previous results are not used in the calculations for a next tone sample. A series approximation of a desired complex sound waveform is achieved by calculating the contributions of twenty-nine time steps back in time. Twenty-nine different address phases are respectively applied to twenty-nine stacked arithmetic units. Each arithmetic unit comprises a first adder that inputs the output of a previous arithmetic unit and the input of the previous arithmetic unit. A second adder inputs the result from the first adder and one of the twenty-nine address phases. The second adder then reads a waveform generator connected to a multiplier that is controlled by a common multiplication factor "B". The output of the twenty-ninth unit produces the desired tone without any of the stacked units feeding back any signals.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: November 26, 1996
    Assignee: ESS Technology, Inc.
    Inventor: Roi N. Peers, Jr.