Patents by Inventor Rok Dittrich

Rok Dittrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7903452
    Abstract: A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external magnetic field having a non-zero angle relative to one another.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: March 8, 2011
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventors: Rok Dittrich, Ulrich Klostermann
  • Patent number: 7719884
    Abstract: According to one embodiment of the present invention, and integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing the memory cell, such that the bias condition increases the stability of the set reference memory cell state.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: May 18, 2010
    Assignees: Qimonda AG, ALTIS Semiconductor, SNC
    Inventor: Rok Dittrich
  • Patent number: 7706176
    Abstract: An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 27, 2010
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventor: Rok Dittrich
  • Publication number: 20090285012
    Abstract: According to one embodiment of the present invention, an integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing the memory cell, such that the bias condition increases the stability of the set reference memory cell state.
    Type: Application
    Filed: May 19, 2008
    Publication date: November 19, 2009
    Inventor: Rok Dittrich
  • Publication number: 20090196088
    Abstract: An integrated circuit may comprise one or more resistive storage cells, wherein each resistive storage cell comprises a resistive storage medium that is switchable between at least a high resistive state and a low resistive state; and a resistance element communicatively coupled to the resistive storage medium in series.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 6, 2009
    Inventors: Rok Dittrich, Jan Keller, Ralf Symanczyk
  • Publication number: 20090190409
    Abstract: An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one monitoring memory cell and at least one memory cell, wherein the at least one monitoring memory cell has a shorter retention time than the at least one memory cell. The cell arrangement further includes a detector to detect the memory status of the at least one monitoring memory cell, a comparator to compare the detected memory status of the at least one monitoring memory cell with a predefined memory status for the at least one monitoring memory cell, and a controller to control a refresh operation of the at least one memory cell dependent from the comparing result.
    Type: Application
    Filed: January 28, 2008
    Publication date: July 30, 2009
    Inventors: Rok Dittrich, Ulrich Klostermann
  • Publication number: 20090175108
    Abstract: An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 9, 2009
    Inventor: Rok Dittrich
  • Patent number: 7532506
    Abstract: An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line current and the second line current, such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that the transition time of the magnetic field is shorter than the time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: May 12, 2009
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventors: Rok Dittrich, Ulrich Klostermann
  • Publication number: 20090073749
    Abstract: An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line current and the second line current, such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that the transition time of the magnetic field is shorter than the time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 19, 2009
    Inventors: Rok Dittrich, Ulrich Klostermann
  • Publication number: 20070297219
    Abstract: A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external magnetic field having a non-zero angle relative to one another.
    Type: Application
    Filed: June 23, 2006
    Publication date: December 27, 2007
    Inventors: Rok Dittrich, Ulrich Klostermann