Patents by Inventor ROKESH JAYASUNDAR

ROKESH JAYASUNDAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10803224
    Abstract: A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salim Shah, Rokesh Jayasundar, Shyam Ramji, Paul G. Villarrubia
  • Publication number: 20200159882
    Abstract: A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.
    Type: Application
    Filed: November 18, 2018
    Publication date: May 21, 2020
    Inventors: Salim Shah, Rokesh Jayasundar, Shyam Ramji, Paul G. Villarrubia
  • Patent number: 10140127
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar, Dung Q. Nguyen, David R. Terry
  • Patent number: 10127047
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar, Dung Q. Nguyen, David R. Terry
  • Publication number: 20180232236
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Application
    Filed: February 18, 2018
    Publication date: August 16, 2018
    Inventors: BRIAN D. BARRICK, SUNDEEP CHADHA, MAUREEN A. DELANEY, THAO T. DOAN, MICHAEL J. GENDEN, ROKESH JAYASUNDAR, DUNG Q. NGUYEN, DAVID R. TERRY
  • Publication number: 20180232230
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 16, 2018
    Inventors: Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar, Dung Q. Nguyen, David R. Terry
  • Patent number: 9952874
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar, Dung Q. Nguyen, David R. Terry
  • Patent number: 9952861
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar, Dung Q. Nguyen, David R. Terry
  • Publication number: 20170168834
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 15, 2017
    Inventors: BRIAN D. BARRICK, SUNDEEP CHADHA, MAUREEN A. DELANEY, THAO T. DOAN, MICHAEL J. GENDEN, ROKESH JAYASUNDAR, DUNG Q. NGUYEN, DAVID R. TERRY
  • Publication number: 20170168822
    Abstract: Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: BRIAN D. BARRICK, SUNDEEP CHADHA, MAUREEN A. DELANEY, THAO T. DOAN, MICHAEL J. GENDEN, ROKESH JAYASUNDAR, DUNG Q. NGUYEN, DAVID R. TERRY