Patents by Inventor Roksana Golizadeh Mojarad
Roksana Golizadeh Mojarad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10729980Abstract: Embodiments described herein provide an apparatus comprising a processor to receive, from a gaming/anti-cheating server, a message comprising a first pixel data set comprising first pixel data for one or more pixels of a watermark generated by the gaming/anti-cheating server, store the first pixel data set in the machine-readable memory, receive, from a gaming system, a frame buffer rendered by the gaming system and comprising the watermark generated by the gaming/anti-cheating server, isolate, from the frame buffer, a second pixel data set comprising second pixel data for one or more pixels corresponding to the first pixel set, and forward an alert to the gaming/anti-cheating server when the second pixel data differs from the first pixel data by an amount that exceeds a threshold. Other embodiments may be described and claimed.Type: GrantFiled: December 27, 2018Date of Patent: August 4, 2020Assignee: INTEL CORPORATIONInventors: Roksana Golizadeh Mojarad, Amin Heydarpour, Selvakumar Panneer, Rahuldeva Ghosh
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Publication number: 20200206635Abstract: Embodiments described herein provide an apparatus comprising a processor to receive, from a gaming/anti-cheating server, a message comprising a first pixel data set comprising first pixel data for one or more pixels of a watermark generated by the gaming/anti-cheating server, store the first pixel data set in the machine-readable memory, receive, from a gaming system, a frame buffer rendered by the gaming system and comprising the watermark generated by the gaming/anti-cheating server, isolate, from the frame buffer, a second pixel data set comprising second pixel data for one or more pixels corresponding to the first pixel set, and forward an alert to the gaming/anti-cheating server when the second pixel data differs from the first pixel data by an amount that exceeds a threshold. Other embodiments may be described and claimed.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Applicant: Intel CorporationInventors: ROKSANA GOLIZADEH MOJARAD, AMIN HEYDARPOUR, SELVADUMAR PANEER, RAHULDEVA GHOSH
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Patent number: 10580973Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).Type: GrantFiled: December 10, 2018Date of Patent: March 3, 2020Assignee: INTEL CORPORATIONInventors: Brian S. Doyle, Kaan Oguz, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, David L. Kencke, Robert S. Chau, Roksana Golizadeh Mojarad
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Publication number: 20190109281Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).Type: ApplicationFiled: December 10, 2018Publication date: April 11, 2019Applicant: INTEL CORPORATIONInventors: BRIAN S. DOYLE, KAAN OGUZ, CHARLES C. KUO, MARK L. DOCZY, SATYARTH SURI, DAVID L. KENCKE, ROBERT S. CHAU, ROKSANA GOLIZADEH MOJARAD
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Patent number: 10158065Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).Type: GrantFiled: July 7, 2014Date of Patent: December 18, 2018Assignee: INTEL CORPORATIONInventors: Brian S. Doyle, Kaan Oguz, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, David L. Kencke, Robert S. Chau, Roksana Golizadeh Mojarad
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Patent number: 9882123Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.Type: GrantFiled: October 24, 2016Date of Patent: January 30, 2018Assignee: Intel CorporationInventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
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Patent number: 9779794Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.Type: GrantFiled: March 26, 2014Date of Patent: October 3, 2017Assignee: INTEL CORPORATIONInventors: Brian S. Doyle, David L. Kencke, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Charles C. Kuo, Roksana Golizadeh Mojarad
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Patent number: 9735348Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.Type: GrantFiled: December 29, 2015Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Elijah V. Karpov, Roksana Golizadeh Mojarad, David L. Kencke, Robert S. Chau
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Patent number: 9728238Abstract: Spin transfer torque memory (STTM) devices with half-metals and methods to write and read the devices are described. For example, a magnetic tunneling junction includes a free magnetic layer, a fixed magnetic layer, and a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer. One or both of the free magnetic layer and the fixed magnetic layer includes a half-metal material at an interface with the dielectric layer.Type: GrantFiled: December 19, 2011Date of Patent: August 8, 2017Assignee: Intel CorporationInventors: Charles C. Kuo, Roksana Golizadeh Mojarad, Brian S. Doyle, David L. Kencke, Kaan Oguz, Robert S. Chau
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Publication number: 20170092846Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).Type: ApplicationFiled: July 7, 2014Publication date: March 30, 2017Applicant: INTEL CORPORATIONInventors: BRIAN S. DOYLE, KAAN OGUZ, CHARLES C. KUO, MARK L. DOCZY, SATYARTH SURI, DAVID L. KENCKE, ROBERT S. CHAU, ROKSANA GOLIZADEH MOJARAD
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Publication number: 20170040530Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.Type: ApplicationFiled: October 24, 2016Publication date: February 9, 2017Inventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
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Perpendicular MTJ stacks with magnetic anisotrophy enhancing layer and crystallization barrier layer
Patent number: 9548441Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.Type: GrantFiled: March 16, 2015Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau -
Publication number: 20160351238Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.Type: ApplicationFiled: March 26, 2014Publication date: December 1, 2016Applicant: INTEL CORPORATIONInventors: BRIAN S. DOYLE, DAVID L. KENCKE, KAAN OGUZ, MARK L. DOCZY, SATYARTH SURI, ROBERT S. CHAU, CHARLES C. KUO, ROKSANA GOLIZADEH MOJARAD
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Patent number: 9478734Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.Type: GrantFiled: May 27, 2015Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
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Patent number: 9472748Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.Type: GrantFiled: January 11, 2016Date of Patent: October 18, 2016Assignee: INTEL CORPORATIONInventors: Charles C. Kuo, Brian S. Doyle, Arijit Raychowdhury, Roksana Golizadeh Mojarad, Kaan Oguz
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Patent number: 9455011Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.Type: GrantFiled: March 25, 2012Date of Patent: September 27, 2016Assignee: Intel CorporationInventors: Arijit Raychowdhury, David Kencke, Brian Doyle, Charles Kuo, James Tschanz, Fatih Hamzaoglu, Yih Wang, Roksana Golizadeh Mojarad
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Patent number: 9437808Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.Type: GrantFiled: October 19, 2015Date of Patent: September 6, 2016Assignee: Intel CorporationInventors: Brian S. Doyle, Charles C. Kuo, David L. Kencke, Roksana Golizadeh Mojarad, Uday Shah
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Publication number: 20160133829Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.Type: ApplicationFiled: December 29, 2015Publication date: May 12, 2016Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Elijah V. Karpov, Roksana Golizadeh Mojarad, David L. Kencke, Robert S. Chau
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Publication number: 20160126452Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.Type: ApplicationFiled: January 11, 2016Publication date: May 5, 2016Applicant: INTEL CORPORATIONInventors: CHARLES C. KUO, BRIAN S. DOYLE, Arijit Raychowdhury, ROKSANA GOLIZADEH MOJARAD, KAAN OGUZ
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Publication number: 20160043302Abstract: Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.Type: ApplicationFiled: October 19, 2015Publication date: February 11, 2016Inventors: Brian S. DOYLE, Charles C. KUO, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Uday SHAH