Abstract: An electronic circuit that multiplies an input signal using primarily digital components so that the resulting circuit can be fabricated consistently by different foundries. The circuit determines a period for the input signal and converts the period to a digital number (e.g., a binary number). An adder is used to determine an average period over a predetermined number of cycles. By determining the average period, voltage fluctuations are cancelled. A multiplier allows for a variable multiplication of the averaged period. A clock generating circuit uses the results obtained by the multiplier to generate a multiplied output signal. Additionally, the input signal is routinely multiplexed with the generated output signal to ensure phase matching.

Abstract: By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for normalization and number format conversion can concurrently be initiated and partially carried out prior to completion of a determination of the number of leading zeros in an expression of a number. The combined count leading zero circuit and shifter provides faster operation which can be completed within one cycle time and hardware architecture simplifications are achieved to reduce required circuit element count and chip space.

Abstract: In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken from the mask generator and an Exclusive-OR function applied to adjacent bits to generate a second mask containing or adjacent to a transition between the portion of the number to be dropped and the portion to be retained in the truncated number. The second mask is applied to different overlapping groups of bits in a portion of the number which contains the least significant bit and the guard bit as determined from the number of bits to be dropped, for example, by shifting out from a shifter, as the number is truncated and rounded to extract a specific bit in each group of bits. By extracting such specific bits using a mask, the extraction process is removed from the critical path of the processor which includes the shifter and the extraction process can proceed in parallel with the shifting process.

Abstract: Signal propagation time through a transmission gate array or multiplexer is significantly reduced and output signal transition time is halved by detecting non-selection of a section of the multiplexer and activating an output circuit, preferably in the form of a logic gate, to respond to a signal passed through a selected section of the transmission gate array or multiplexer. Specifically, upon non-selection of a section, an appropriate logic-valued signal at a reference voltage is propagated on an internal node of the multiplexer to the input of the output circuit to precondition or activate the output circuit. Since this signal is strongly tied to the reference voltage, the response of the output circuit is improved in both response time and transition time. Further, capacitance of internal nodes of the multiplexer is insulated or isolated from the inputs to the multiplexer, avoiding trade-offs between circuit performance and wiring congestion.

Abstract: In a mask generator, decoders are provided for decoding respective portions of an input bit string into an intermediate string, and first and second selection signals. The intermediate string is placed into a first mask by a primary selection stage according to the first selection signals. The first mask is placed into a second mask by a secondary selection stage according to the second selection signals. The decoders are implemented using combinational logic, and the primary selectors are implemented using multiplexer and phase inverter circuits. Sixteen bit mask generation is realized from a 4-bit input string using only two decoders and a primary selector. Sixty-four bit mask generation is realized using a 6-bit input bit string and a secondary selector. The first and second masks contain two contiguous series of 1s and 0s. Parallel arrangements of mask generators are disclosed so that alternating series of 1s and 0s can be placed in output masks.