Abstract: An electronic-hydraulic control device for gearboxes of vehicles, preferably motor vehicles, includes a housing in which an electronic unit for controlling magnetic valves is accommodated. The valves are supplied with a pressure medium. The housing has a magnetic housing part in which magnetic parts of the magnetic valves and the electronic unit of the control device are accommodated and which lies outside the gearbox, and a hydraulic housing part in which hydraulic parts of the magnetic valves are located and which is positioned at least partially inside the gearbox housing.

Abstract: This invention relates to a method of loading Java ClassFiles on to a Java Virtual Machine. On a regular JVM the ClassFile are loaded as and when required. In this specification there is described a method of implementing an object oriented program language such as Java on a computer. The method comprises identifying a class, one of the basic building blocks of the language, which is not within the program domain, that is not loaded into the Java a Virtual Machine. Next it introduces to the program domain only the minimum components of the class which are necessary for commencing processing of the class. The class may comprise several blocks of data representing the methods of the class, since the class may only have been identified because one of the methods within the class was referenced then only the block of data representing this method is loaded into the Java Virtual Machine along with the other essential components of the class.

Abstract: A voltage regulator for converting an input voltage (Vi) into an output voltage (Vo). The input voltage may be burdened with a ripple. The output voltage (Vo) supplied by the voltage regulator is virtually free from ripple. The voltage regulator comprises an input terminal (1) for receiving the input voltage (Vi), an output terminal for supplying the output voltage (Vo) in response to the input voltage (Vi), and current limiting means for limiting the maximum absolute value of an output current (Io) taken from the output terminal (2). The current limiting means comprise a field effect transistor (TCL). The voltage regulator further comprises a first current mirror (CM1) comprising transistors (T11, T12), a second current mirror (CM2) comprising transistors (T13, T14), and a third current mirror comprising transistors (T15, T16). In a typical operation, the field effect transistor (TCL) is in the linear region and thus behaves like a resistance.

Abstract: The control device has a control circuit and a pressure sensor for measuring the hydraulic pressure in the gearbox. The control circuit and the pressure sensor are accommodated in a common housing. The housing has a metallic baseplate which is connected in a pressure tight fashion to a hydraulic unit of the gearbox and is provided with a bore hole through which pressure is applied to the pressure sensor. A carrier for the pressure sensor has a cylinder-like projection which is pressed into the bore hole in such a way that a pressure tight and frictionally locking connection is produced between the carrier and the baseplate as a result of the displacement of material. The pressure sensor can also be used to measure the intake vacuum of an engine.

Abstract: A method of displaying clustered data points in detail and in context within a data set. The method includes the step of identifying one or more clustered sets of data points within a data set. The data set includes a plurality of data points. The method also includes the steps of determining a respective data range segment for each cluster of data points, where each data range segment has a boundary and a scale interval, and displaying the data points in each segment such that each segment is mutually distinguishable. Where two or more data range segments are determined, the scale interval value for one of the data range segments is modifiable to differ from one or more of the other data range segments.

Abstract: By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for normalization and number format conversion can concurrently be initiated and partially carried out prior to completion of a determination of the number of leading zeros in an expression of a number. The combined count leading zero circuit and shifter provides faster operation which can be completed within one cycle time and hardware architecture simplifications are achieved to reduce required circuit element count and chip space.

Abstract: In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken from the mask generator and an Exclusive-OR function applied to adjacent bits to generate a second mask containing or adjacent to a transition between the portion of the number to be dropped and the portion to be retained in the truncated number. The second mask is applied to different overlapping groups of bits in a portion of the number which contains the least significant bit and the guard bit as determined from the number of bits to be dropped, for example, by shifting out from a shifter, as the number is truncated and rounded to extract a specific bit in each group of bits. By extracting such specific bits using a mask, the extraction process is removed from the critical path of the processor which includes the shifter and the extraction process can proceed in parallel with the shifting process.

Abstract: The present invention provides a system and method for displaying on a display device (20) connectable to the system a visual representation of a physical environment, such as a virtual office. The system includes display controls (30) for displaying objects in the physical environment including a data management object, one or more data objects representing data sources, and one or more output objects representing paths through which data from a data source can be presented to a user. A user-operated device (50) is connectable to the system to allow a user to interact with the objects. The system includes data receiving means (70), responsive to signals from the user-operated device (50) indicating user association of one or more data objects with the data management object, to access the data represented by the one or more associated data objects.

Abstract: Signal propagation time through a transmission gate array or multiplexer is significantly reduced and output signal transition time is halved by detecting non-selection of a section of the multiplexer and activating an output circuit, preferably in the form of a logic gate, to respond to a signal passed through a selected section of the transmission gate array or multiplexer. Specifically, upon non-selection of a section, an appropriate logic-valued signal at a reference voltage is propagated on an internal node of the multiplexer to the input of the output circuit to precondition or activate the output circuit. Since this signal is strongly tied to the reference voltage, the response of the output circuit is improved in both response time and transition time. Further, capacitance of internal nodes of the multiplexer is insulated or isolated from the inputs to the multiplexer, avoiding trade-offs between circuit performance and wiring congestion.

Abstract: In a mask generator, decoders are provided for decoding respective portions of an input bit string into an intermediate string, and first and second selection signals. The intermediate string is placed into a first mask by a primary selection stage according to the first selection signals. The first mask is placed into a second mask by a secondary selection stage according to the second selection signals. The decoders are implemented using combinational logic, and the primary selectors are implemented using multiplexer and phase inverter circuits. Sixteen bit mask generation is realized from a 4-bit input string using only two decoders and a primary selector. Sixty-four bit mask generation is realized using a 6-bit input bit string and a secondary selector. The first and second masks contain two contiguous series of 1s and 0s. Parallel arrangements of mask generators are disclosed so that alternating series of 1s and 0s can be placed in output masks.

Abstract: Anhydrous metal dithionite compositions are stabilized by 0.1 to 5% by weight of the composition of one or more of vanillin, ethyl vanillin and benzoin.

Abstract: A method of producing a bas-relief with a motif which varies with the light, characterized in that the original motif to be reproduced is divided into a grid. The intensity of the grey in each of the divisions of the grid is measured. A numerical value is assigned to each division. The numerical value represents an intensity of grey and corresponds to an element of the bas-relief. The elements of the bas-relief, in accordance with the way in which the grid is divided, are placed side by side in a manner such that the light rays simultaneously make surface shadow spots appear on each element of the bas-relief in accordance with the intensity of the grey of the original motif. The composition of the spots is seen by viewing the bas-relief from a distance and reproduces the original motif.